• intel/microarchitectures/bonnell
  Note that the L1 cache for data and instructions were originally both 32 KiB (8-way), however due to power restrictions, the ...ons with up to 3 prefixes each cycle (considerably longer for more complex instructions).
  38 KB (5,468 words) - 20:29, 23 May 2019
• intel/microarchitectures/sandy bridge (client)
  ====New instructions ==== Sandy Bridge introduced a number of {{x86|extensions|new instructions}}:
  84 KB (13,075 words) - 00:54, 29 December 2020
• intel/microarchitectures/skylake (client)
  ====New instructions ==== ...croarchitectures/skylake_(server)#New instructions|l1=Server Skylake's New instructions}}
  79 KB (11,922 words) - 06:46, 11 November 2022
• intel/microarchitectures/coffee lake
  ! Execution Unit !! # of Units !! Instructions ...en verbatim from the Intel manual. Execution unit mapping to {{x86|MMX|MMX instructions}} are not included.
  30 KB (4,192 words) - 13:48, 10 December 2023
• amd/microarchitectures/zen
  ...location/die size, clock/frequency restriction, power limitations, and new instructions to implement. ** Large μop cache (2K instructions)
  79 KB (12,095 words) - 15:27, 9 June 2023
• amd/microarchitectures/zen 2
  ==== New instructions ==== Zen 2 introduced a number of new [[x86]] instructions:
  57 KB (8,701 words) - 22:11, 9 October 2022
• phytium/microarchitectures/xiaomi
  ...ack (RAS) for speculative subroutine return and a 2K-entry BTB. Up to four instructions can be fetches each cycle into the instruction buffer which is 32 entries i ...h cycle, up to four instructions can be renamed each cycle, and up to four instructions can be dispatched each cycle. Everything is done [[in-order]] up to this po
  7 KB (940 words) - 00:12, 8 March 2021
• acorn/microarchitectures/arm1
  ...w access [[DRAM]]. The ARM1's pipeline consists of 3 stages (although some instructions may take as much as 5 cycles): ...execution, it therefore holds a number of instruction sufficient to ensure instructions are always executing at all cycles on all stages.
  12 KB (1,886 words) - 12:56, 14 January 2021
• intel/microarchitectures/merced
  | inst = <!-- yes for instructions options --> ** Two bundles, each containing three instructions, fetched from the instruction cache every cycle
  7 KB (978 words) - 21:16, 20 January 2021
• macro-operation fusion
  ...] are merged into a single macro-operation prior or during decoding. Those instructions are later decoded into fused-µOPs. ...struction typically remains fused throughout its lifetime. Therefore fused instructions can represent more work with fewer bits, free up execution units, tracking
  11 KB (1,614 words) - 23:01, 8 May 2020
• acorn/microarchitectures/arm2
  ==== New instructions ==== ARM2 introduces a number of new instructions to deal with the new features:
  14 KB (2,093 words) - 04:42, 10 July 2018
• x86/avx-512
  ; '''AVX512CD''' - {{x86|AVX512CD|'''AVX-512 Conflict Detection Instructions'''}} ; '''AVX512PF''' - {{x86|AVX512PF|'''AVX-512 Prefetch Instructions'''}}
  83 KB (13,667 words) - 15:45, 16 March 2023
• intel/microarchitectures/goldmont plus
  ** VP9 10-bit Profile2 hardware decoding ====New instructions ====
  9 KB (1,128 words) - 13:28, 17 July 2023
• mirc/identifiers/$sslcertsha256
  ...ring could be visible. If you entered your password as string1:string2 the decoding of that mime would be: ...command-line program which can be a little hard to get used to, but these instructions will walk you through it, and you can use commands that you can paste into
  22 KB (3,851 words) - 22:19, 11 November 2021
• samsung/microarchitectures/m1
  *** Most instructions map to a single µOP, with a few exceptions ...erating addresses. There are three cycles for [[instruction fetch|fetching instructions]] from the [[instruction cache]] and delivering them to the [[instruction q
  13 KB (1,962 words) - 14:48, 21 February 2019
• samsung/microarchitectures/m3
  ...erating addresses. There are three cycles for [[instruction fetch|fetching instructions]] from the [[instruction cache]] and delivering them to the [[instruction q ...ruction streams, the fetching of instructions, and the code of the [[ARM]] instructions into [[micro-operations]] to be executed by the back-end.
  20 KB (3,149 words) - 10:44, 15 February 2020
• cavium/microarchitectures/vulcan
  Vulcan's front-end is tasked with fetching instructions from a ready thread instruction stream and feeding them into the decode in ...in the pipeline. The instruction stream is decomposed into its constituent instructions where they are queued to go for the [[instruction decode|decoder]]. The que
  17 KB (2,449 words) - 22:11, 4 October 2019
• amd/microarchitectures/zen 4
  ...with a stack optimizer, multiple caches including an Op cache for decoded instructions and prefetchers for code and data, four integer/address and two floating po * {{x86|AVX-512}} instructions support, 256-bit data path<ref name="ryzen-7000-preview"/>
  13 KB (1,821 words) - 19:28, 13 November 2023
• nec/microarchitectures/sx-aurora
  ...SPU on the SX-Aurora is four wide - capable of fetching and decoding four instructions per cycle. NEC stated that the SPU features a sophisticated [[branch predic ...ddress for the vector accesses. Typically this is done prior to the vector instructions being sent to the VPU in order to ensure that the data is ready by that tim
  16 KB (2,497 words) - 13:30, 15 May 2020
• intel/microarchitectures/sunny cove
  ** Wider decoding width with an additional simple decoder is added (from 3 simple + 1 complex ==== New instructions ====
  34 KB (5,187 words) - 06:27, 17 February 2023

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