• intel/microarchitectures/sandy bridge (client)
  ...hile saving power and bandwidth. Partitioning the data also helps simplify coherency as well as reducing localized contentions and hot spots. ...to prevent hot spots. The cache box is responsible for the maintaining of coherency and ordering between requests. Because the LLC slices are fully inclusive,
  84 KB (13,075 words) - 00:54, 29 December 2020
• intel/microarchitectures/skylake (client)
  ...in terms of coherency (note that no flushing is thus necessary to maintain coherency), ordering, or other organizational details. For optimal graphics performan
  79 KB (11,922 words) - 06:46, 11 November 2022
• intel/xeon e5
  ==== Cache Coherency ====
  11 KB (1,395 words) - 08:36, 4 November 2020
• intel/microarchitectures/gen9
  *** Improved cache coherency performance
  33 KB (4,255 words) - 17:41, 1 November 2018
• phytium/microarchitectures/xiaomi
  * Large scale cache coherency * Global cache coherency
  7 KB (940 words) - 00:12, 8 March 2021
• intel/microarchitectures/skylake (server)
  === Cache Coherency === ...snoop, home snoop, and directory) have been reduced to just directory-base coherency. This also alleviates the implementation complexity (which is already compl
  52 KB (7,651 words) - 00:59, 6 July 2022
• microsoft/scorpio engine
  ...tween the [[memory controllers]] and the CPUs and GPU. The bus maintains [[coherency]] between the CPU cores and the GPU. For the GPU, each of the 12 [[memory c
  15 KB (2,390 words) - 02:54, 17 May 2023
• pezy/pezy-scx
  ...ch is used by the code to track processes. The PEs do not maintain [[cache-coherency]] and there is no per-PE [[data cache]]. Complex instructions are processed
  6 KB (838 words) - 09:33, 9 May 2019
• nvidia/tegra/xavier
  ...and [[ASIL]] level C. The CPU cluster is fully [[cache coherent]] and the coherency is extended to all the other [[accelerators]] on-chip.
  8 KB (1,263 words) - 03:08, 9 December 2019
• zhaoxin/microarchitectures/wudaokou
  ...bar reduces the latency and provides facilities for control flow and cache coherency. Going through the crossbar is also the newly integrated graphics processor
  9 KB (1,134 words) - 13:02, 17 June 2019
• samsung/coherent interconnect
  ...oduced with the introduction of the [[Exynos 8 Octa]] which provides cache coherency and management between the generic [[ARM Holdings|ARM]] {{armh|Cortex-A53|l
  563 bytes (71 words) - 01:43, 5 February 2018
• intel/mesh interconnect architecture
  ...('''CHA''') - a unit found inside the core tiles that maintains the cache coherency between tiles. The CHA also interfaces with the CMS
  7 KB (1,071 words) - 12:59, 2 November 2021
• ccix
  ...cache coherent framework for [[heterogeneous system architecture]]s. Cache coherency is automatically maintained at all time between the [[central processing un ...eads and writes, provides a mapping for the on-chip architecture-dependent coherency protocols (e.g., AMBA CHI/ACE). This layer also defines the cache state (e.
  4 KB (614 words) - 09:54, 7 October 2018
• arm holdings/microarchitectures/neoverse n1
  *** [[Modified Exclusive Shared Invalid]] (MESI) coherency
  7 KB (980 words) - 13:46, 18 February 2023
• arm holdings/microarchitectures/cortex-a76
  *** [[Modified Exclusive Shared Invalid]] (MESI) coherency
  14 KB (2,183 words) - 17:15, 17 October 2020
• arm holdings/microarchitectures/cortex-a77
  *** [[Modified Exclusive Shared Invalid]] (MESI) coherency
  17 KB (2,555 words) - 06:08, 16 June 2023
• arm holdings/microarchitectures/cortex-a78
  *** [[Modified Exclusive Shared Invalid]] (MESI) coherency
  21 KB (3,067 words) - 09:25, 31 March 2022
• nvidia/microarchitectures/carmel
  ...an 8-core cluster made of 4 core duplexes. The entire complex has [[cache coherency]] as well as an I/O coherent memory subsystem which is designed for communi
  2 KB (280 words) - 11:27, 30 April 2019
• phytium/microarchitectures/mars i
  ...''' ('''DCU''') which are in charge of maintaining directory-based [[cache coherency]] and one routing cell for managing the inter-panel communication. ...rence protocol which implements a distributed directory-based global cache coherency across all the panels. Hawk is a [[MOESI]]-like package-based protocol. The
  6 KB (809 words) - 16:49, 15 October 2019
• hisilicon/microarchitectures/taishan v110
  ...PCIe Gen 4 lanes provided per socket with [[CCIX]] support, enabling cache coherency. ...tes three Hydra interface ports. The Hydra interface facilitates the cache coherency between the dies on the chip. Every link supports 240 Gb/s (30 GB/s) of pea
  7 KB (947 words) - 10:20, 9 September 2022

View (previous 20 | next 20) (20 | 50 | 100 | 250 | 500)