• intel/microarchitectures/sandy bridge (client)
  ...entirely redesigned to incorporate a new decoded pipeline using a new µOP cache. The back-end is an entirely new PRF-based renaming architecture with a con * New last level cache architecture
  84 KB (13,075 words) - 00:54, 29 December 2020
• intel/microarchitectures/skylake (client)
  |side cache=128 MiB |side cache per=package
  79 KB (11,922 words) - 06:46, 11 November 2022
• intel/microarchitectures/coffee lake
  * IPC improvement from larger cache for various workloads, but actual core is unchanged ** 50% larger [[last level cache]] (up to 12 MiB, from 8 MiB)
  30 KB (4,192 words) - 13:48, 10 December 2023
• amd/microarchitectures/zen
  ** Large μop cache (2K instructions) * Cache system
  79 KB (12,095 words) - 15:27, 9 June 2023
• cavium/microarchitectures/cnmips
  | cache = Yes | {{cavium|Octeon Plus}} || Second generation (higher clock, bigger cache)
  7 KB (870 words) - 19:38, 23 June 2017
• amd/cores/milan
  ...es by <abbr title="Store Keeping Unit">SKU</abbr>) which share a 32 MiB L3 cache with 46 cycles average latency, doubling the L3 capacity available to one c ...me "Trento". These processors will use a different I/O die with additional coherent {{amd|Infinity Fabric}} links to attach accelerators. They will be used in
  19 KB (2,734 words) - 01:26, 31 May 2021
• amd/infinity fabric
  ...y controller and I/O hub) are routed through the SDF. A key feature of the coherent data fabric is that it's not limited to a single die and can extend over mu ...e '''Cache-Coherent Master''' ('''CCM''') which provides the mechanism for coherent data transports between cores. There is also a single '''I/O Master/Slave''
  8 KB (1,271 words) - 21:50, 18 August 2020
• intel/microarchitectures/skylake (server)
  ...LFLUSHOPT</code>}} - Flush & Invalidates memory operand and its associated cache line (All L1/L2/L3 etc..) * {{x86|CLWB|<code>CLWB</code>}} - Force cache line write-back without flush
  52 KB (7,651 words) - 00:59, 6 July 2022
• intel/microarchitectures/cascade lake
  * Cache ** L0 µOP cache:
  32 KB (4,535 words) - 05:44, 9 October 2022
• nvidia/tegra/xavier
  ...afety [[ISO-26262]] and [[ASIL]] level C. The CPU cluster is fully [[cache coherent]] and the coherency is extended to all the other [[accelerators]] on-chip. ...on for connecting a [[discrete graphics processor]] to Xavier in a [[cache coherent]] manner. Xavier has PCIe Gen 4.0 support (16 GT/s). It's worth noting that
  8 KB (1,263 words) - 03:08, 9 December 2019
• samsung/exynos/8890
  ...ore cluster. Communication is done over Samsung's cache-coherent {{samsung|Coherent Interconnect}} (SCI). == Cache ==
  6 KB (800 words) - 05:21, 25 January 2022
• samsung/coherent interconnect
  {{samsung title|Samsung Coherent Interconnect (SCI)}} ...t introduced with the introduction of the [[Exynos 8 Octa]] which provides cache coherency and management between the generic [[ARM Holdings|ARM]] {{armh|Co
  563 bytes (71 words) - 01:43, 5 February 2018
• apm/microarchitectures/skylark
  ** Coherent network improved for large core count * Cache
  3 KB (356 words) - 20:13, 25 September 2018
• nvidia/nvlink
  ...y system [[interconnect architecture]] that facilitates [[memory coherence|coherent]] data and control transmission accross multiple [[Nvidia]] [[GPU]]s and su ...VLink now has [[cache coherence]] support, allowing the CPU to efficiently cache GPU memory, significantly improving latencies and thus performance. NVLink
  9 KB (1,518 words) - 04:38, 12 April 2024
• cavium/microarchitectures/vulcan
  *** Half L2 Cache Size (256 KiB, down form 512 KiB) * Cache
  17 KB (2,449 words) - 22:11, 4 October 2019
• ccix
  {{title|Cache Coherent Interconnect for Accelerators (CCIX)}}{{interconnect arch}} ...processor]] and the various [[accelerators]] in the system through a cache-coherent extension to standard [[PCIe]].
  4 KB (614 words) - 09:54, 7 October 2018
• amd/packages/socket tr4
  ...brics of each processor on dual-socket server platforms. S-Link is a cache coherent link to {{abbr|CCIX}} memory expanders. XGBE is a backplane Ethernet link w
  86 KB (17,313 words) - 02:48, 13 March 2023
• amd/packages/socket sp3
  ...cache.<!--Naffziger2020--> GN-B1 CCDs contain one CCX with 32&nbsp;MiB L3 cache, the GMI2 signals are routed to the chip edge. These are serial, single-end S-Link is a cache coherent link to {{abbr|CCIX}} memory expanders introduced on Type-1 processors. As
  110 KB (21,122 words) - 02:46, 13 March 2023
• intel/xeon gold/6138p
  ...l|UPI}} links from the CPU for the FPGA, providing the FPGA with a [[cache coherent]] link to the CPU. == Cache ==
  6 KB (881 words) - 01:14, 24 May 2019
• arm holdings/microarchitectures/neoverse n1
  ** Designed for the [[Coherent Mesh Network 600]] (CMN-600) mesh interconnect The Neoverse N1 has a private L1I, L1D, and L2 cache.
  7 KB (980 words) - 13:46, 18 February 2023

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