• intel/microarchitectures/sandy bridge (client)
  ...entirely redesigned to incorporate a new decoded pipeline using a new µOP cache. The back-end is an entirely new PRF-based renaming architecture with a con * New last level cache architecture
  84 KB (13,075 words) - 00:54, 29 December 2020
• intel/microarchitectures/skylake (client)
  |side cache=128 MiB |side cache per=package
  79 KB (11,922 words) - 06:46, 11 November 2022
• intel/xeon e5
  ==== Cache Coherency ====
  11 KB (1,395 words) - 08:36, 4 November 2020
• intel/microarchitectures/gen9
  ...vels of performance. Some models also support an additional [[eDRAM]] side cache. ...ontains 2 slices with 48 execution units. Has an additional [[eDRAM]] side cache.
  33 KB (4,255 words) - 17:41, 1 November 2018
• phytium/microarchitectures/xiaomi
  |cache=Yes * Large scale cache coherency
  7 KB (940 words) - 00:12, 8 March 2021
• intel/microarchitectures/skylake (server)
  ...LFLUSHOPT</code>}} - Flush & Invalidates memory operand and its associated cache line (All L1/L2/L3 etc..) * {{x86|CLWB|<code>CLWB</code>}} - Force cache line write-back without flush
  52 KB (7,651 words) - 00:59, 6 July 2022
• microsoft/scorpio engine
  == Cache == .../microarchitectures/enhanced_jaguar#Memory_Hierarchy|l1=Enhanced Jaguar § Cache}}
  15 KB (2,390 words) - 02:54, 17 May 2023
• pezy/pezy-scx
  ...The PEs do not maintain [[cache-coherency]] and there is no per-PE [[data cache]]. Complex instructions are processed by the Special Function Units (SFU) l ...2 KiB of [[level 1 data cache]]. Each '''City''' is made of 64 KiB of [[L2 cache]], a number of special function units, and 4 smaller blocks called "Village
  6 KB (838 words) - 09:33, 9 May 2019
• nvidia/tegra/xavier
  ...and [[ASIL]] level C. The CPU cluster is fully [[cache coherent]] and the coherency is extended to all the other [[accelerators]] on-chip. ...irection for connecting a [[discrete graphics processor]] to Xavier in a [[cache coherent]] manner. Xavier has PCIe Gen 4.0 support (16 GT/s). It's worth no
  8 KB (1,263 words) - 03:08, 9 December 2019
• zhaoxin/microarchitectures/wudaokou
  * Cache ** L1D Cache
  9 KB (1,134 words) - 13:02, 17 June 2019
• samsung/coherent interconnect
  ...oduced with the introduction of the [[Exynos 8 Octa]] which provides cache coherency and management between the generic [[ARM Holdings|ARM]] {{armh|Cortex-A53|l
  563 bytes (71 words) - 01:43, 5 February 2018
• intel/mesh interconnect architecture
  ...('''CHA''') - a unit found inside the core tiles that maintains the cache coherency between tiles. The CHA also interfaces with the CMS
  7 KB (1,071 words) - 12:59, 2 November 2021
• ccix
  {{title|Cache Coherent Interconnect for Accelerators (CCIX)}}{{interconnect arch}} ...ntral processor]] and the various [[accelerators]] in the system through a cache-coherent extension to standard [[PCIe]].
  4 KB (614 words) - 09:54, 7 October 2018
• arm holdings/microarchitectures/neoverse n1
  The Neoverse N1 has a private L1I, L1D, and L2 cache. * Cache
  7 KB (980 words) - 13:46, 18 February 2023
• arm holdings/microarchitectures/cortex-a76
  The Cortex-A76 has a private L1I, L1D, and L2 cache. * Cache
  14 KB (2,183 words) - 17:15, 17 October 2020
• arm holdings/microarchitectures/cortex-a77
  ** New [[L0]] MOP cache The Cortex-A77 has a private L1I, L1D, and L2 cache.
  17 KB (2,555 words) - 06:08, 16 June 2023
• arm holdings/microarchitectures/cortex-a78
  ** New 32 KiB [[L1I cache]] option (from 64 KiB only) ** New 32 KiB [[L1D cache]] option (from 64 KiB only)
  21 KB (3,067 words) - 09:25, 31 March 2022
• nvidia/microarchitectures/carmel
  * Cache ...an 8-core cluster made of 4 core duplexes. The entire complex has [[cache coherency]] as well as an I/O coherent memory subsystem which is designed for communi
  2 KB (280 words) - 11:27, 30 April 2019
• phytium/microarchitectures/mars i
  ...s are interconnected with a 2-dimensional mesh network-on-a-chip [[level 2 cache]] with 4 MiB per panel for a total of 32 MiB. ...uses 8 such chips connected to the main die providing 16 MiB of [[level 3 cache]] for a total of 128 MiB as well as 8 dual-channel DDR3-1600 [[memory contr
  6 KB (809 words) - 16:49, 15 October 2019
• hisilicon/microarchitectures/taishan v110
  * Cache ** L1I Cache
  7 KB (947 words) - 10:20, 9 September 2022

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