• intel/microarchitectures/saltwell
  === Memory Hierarchy === ** Non-Cache Shared State Memory
  7 KB (872 words) - 19:42, 30 November 2017
• intel/microarchitectures/sandy bridge (client)
  ** Memory Subsystem * Integrated Memory Controller
  84 KB (13,075 words) - 00:54, 29 December 2020
• intel/microarchitectures/skylake (client)
  ** Memory Subsystem * Memory
  79 KB (11,922 words) - 06:46, 11 November 2022
• amd/microarchitectures/zen
  * <code>{{x86|SMAP}}</code> - Supervisor Mode Access Prevention === Memory Hierarchy ===
  79 KB (12,095 words) - 15:27, 9 June 2023
• amd/microarchitectures/zen 2
  ** Memory subsystem * <code>{{x86|MCOMMIT}}</code> - Commit stores to memory
  57 KB (8,701 words) - 22:11, 9 October 2022
• amd/cores/milan
  ...7001}} "{{\\|Naples}}" series CPUs. "Type-0" boards designed for the lower memory and PCIe bus frequencies of "Naples" processors are not supported.<ref name ...7091 "HPC Tuning for EPYC 7003" labels the die as "14nm". --> Apart of the memory controllers and I/O facilites described below it integrates an {{amd|secure
  19 KB (2,734 words) - 01:26, 31 May 2021
• x86/avx-512
  ...g at the least significant byte of the register, and vectors are stored in memory LSB to MSB regardless of vector size and element type. Some instructions gr ...in x86-64 mode. In other modes SSE, AVX, and AVX-512 instructions can only access the first eight registers.
  83 KB (13,667 words) - 15:45, 16 March 2023
• intel/microarchitectures/skylake (server)
  ** Memory Subsystem * Memory
  52 KB (7,651 words) - 00:59, 6 July 2022
• intel/microarchitectures/cascade lake
  * "''L''" suffix indicates the SKU is a large memory (4.5 TiB) tier SKU * "''M''" suffix indicates the SKU is a medium memory (2 TiB) tier SKU
  32 KB (4,535 words) - 05:44, 9 October 2022
• samsung/microarchitectures/m3
  **** new fuse address generation and memory µOP support ** Memory subsystem
  20 KB (3,149 words) - 10:44, 15 February 2020
• greenwaves/gap8
  ...full set of drivers for both of those operating systems in order to allow access to all the GAP8 peripherals. ...networks]] (CNNs). It does one cycle 5x5 convolution. HWCE shares the same memory with the rest of the cluster. GreenWaves has software libraries for Deep Le
  6 KB (981 words) - 14:11, 28 February 2018
• ccix
  ...ntral processor]] and the various [[accelerators]] in the system through a cache-coherent extension to standard [[PCIe]]. * CCIX Protocol Layer - coherency protocol that manages memory reads and writes, provides a mapping for the on-chip architecture-dependent
  4 KB (614 words) - 09:54, 7 October 2018
• amd/packages/socket sp3
  ...high performance server processors. It supports eight channels of [[DDR4]] memory and eight 16-lane PCIe I/O links. Socket SP3 succeeded {{\\|Socket G34}} an ...signated for Ryzen Threadripper workstation processors which support eight memory channels and both UDIMM and RDIMM types.
  110 KB (21,122 words) - 02:46, 13 March 2023
• arm holdings/microarchitectures/cortex-a76
  === Memory Hierarchy === ...on units can be grouped into three categories: integer, advanced SIMD, and memory.
  14 KB (2,183 words) - 17:15, 17 October 2020
• arm holdings/microarchitectures/cortex-a77
  * Memory subsystem ** issue queue (IQ) is now unified for the memory subsystem
  17 KB (2,555 words) - 06:08, 16 June 2023
• arm holdings/microarchitectures/cortex-a78
  **** New irregular access pattern detection * Memory subsystem
  21 KB (3,067 words) - 09:25, 31 March 2022
• nanotube-ram
  ...nce-change]] [[memory-class storage|memory-class storage]] [[random access memory|RAM]]. NRAM is proprietary technology developed by [[Nantero]] licenseable ...underlying device and substrate need not matter. It is [[resistance-change memory]] meaning an "off" state is a result of high [[resistance]] while an "on" s
  6 KB (1,010 words) - 02:42, 31 January 2019
• x86/persistent memory extensions
  {{x86 title|Persistent Memory Extensions}}{{x86 isa main}} ...ructions designed to improve the usability of working with [[storage-class memory]].
  2 KB (336 words) - 20:08, 13 May 2021
• intel/microarchitectures/sunny cove
  * Memory subsystem * {{x86|TME|<code>TME</code>}} - Total Memory Encryption
  34 KB (5,187 words) - 06:27, 17 February 2023
• x86/clzero
  ...LZERO is weakly-ordered with respect to other instructions that operate on memory. It executes at any privilege level and performs all the segmentation and p ...cache line without a memory access, and should not be used to quickly zero memory.
  2 KB (325 words) - 01:43, 4 December 2019

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