• mips/mips32 instruction set
  ** [[#Branch instructions|Branch Instructions]] ** [[#Branch instructions|Branch Instructions]]
  18 KB (2,445 words) - 08:24, 9 November 2019
• mirc/regex
  | start of alternative branch
  27 KB (4,356 words) - 20:17, 29 June 2021
• amd/am2900
  | {{\|AM29803A}} || 16-way branch control unit for use with {{\|AM2909A}} || 16
  9 KB (1,061 words) - 22:55, 18 June 2019
• boolean algebra
  ...ean algebra''' (or less commonly '''symbolic logic''') is a [[instance of::branch of algebra]] that deals with only two logic values - [[0]] (corresponding t
  32 KB (5,239 words) - 01:23, 19 May 2016
• Property:instance of
  ** [[allows value::branch of algebra]]
  2 KB (189 words) - 13:28, 11 August 2018
• intel/microarchitectures/bonnell
  ===== Branch predictor ===== ...able has 4096 entries and is [[competitively shared]] between threads. The branch buffer target has 128 entries (4-way by 32 sets). While [[unconditional jum
  38 KB (5,468 words) - 20:29, 23 May 2019
• intel/microarchitectures/saltwell
  * Double the size of the branch prediction history table === Branch Prediction ===
  7 KB (872 words) - 19:42, 30 November 2017
• intel/microarchitectures/silvermont
  ...al-issue design; however it has a pipeline that is 2 stages shorter with a branch misprediction penalty of 3 cycles lower. Silvermont is the first microarchi ...ction of out-of-order execution, silvermont's more aggressive fetching and branch prediction mean stalled instructions do not clog the entire pipeline as it
  9 KB (1,160 words) - 09:35, 25 September 2019
• intel/microarchitectures/haswell (client)
  ...which has 40 entries, 20 for each thread. Haswell continued to improve the branch misses although the exact details have not been made public. ...heduler resources get allocated as well - this includes stores, loads, and branch buffer entries. Note that due to how dependencies are handled, there may be
  27 KB (3,750 words) - 06:57, 18 November 2023
• intel/microarchitectures/sandy bridge (client)
  *** Redesigned branch prediction ...ont-end of Sandy Bridge is the entirely new [[µOP cache]], the overhauled branch predictor and further decoupling of the front-end, and the improved macro-o
  84 KB (13,075 words) - 00:54, 29 December 2020
• intel/microarchitectures/skylake (client)
  *** Improved [[branch prediction unit]] ...ream than in previous architectures. The intimate improvements done in the branch predictor were not further disclosed by Intel.
  79 KB (11,922 words) - 06:46, 11 November 2022
• exponential technology/x704
  ...ger or floating point, but not both), a single load/store operation, and a branch instruction.
  8 KB (1,228 words) - 20:49, 2 June 2019
• intel/microarchitectures/coffee lake
  <tr><td>Branch</td></tr>
  30 KB (4,192 words) - 13:48, 10 December 2023
• amd/microarchitectures/k6
  * Branch Predictor ** 2-level predictor with 8192 entry branch history table
  4 KB (578 words) - 18:57, 22 May 2019
• amd/microarchitectures/k9
  ...ribed by Alsup as: "K9 fetched 8 instructions every other cycle and made 2 branch predictions associated with 3 next fetch addresses every other cycle. K9 is
  2 KB (287 words) - 17:28, 1 December 2018
• amd/microarchitectures/zen
  ** Branch Predictor *** Improved branch mispredictions
  79 KB (12,095 words) - 15:27, 9 June 2023
• amd/microarchitectures/zen 2
  *** Improved [[branch prediction unit]] ...operation, the front-end throughput was improved. AMD reported that the [[branch prediction unit]] has been reworked. This includes improvements to the [[pr
  57 KB (8,701 words) - 22:11, 9 October 2022
• intel/microarchitectures/gen9.5
  ...VFE unit and for spawning child threads (either leaf-node child threads or branch-node parent thread). ...le of integer, single and double precision floating point operations, SIMD branch capability, logical operations, transcendental operations, and other miscel
  29 KB (3,752 words) - 13:14, 19 April 2023
• intel/microarchitectures/gen9
  ...VFE unit and for spawning child threads (either leaf-node child threads or branch-node parent thread). ...le of integer, single and double precision floating point operations, SIMD branch capability, logical operations, transcendental operations, and other miscel
  33 KB (4,255 words) - 17:41, 1 November 2018
• ibm/microarchitectures/power9
  * Improved branch prediction ! Fetch/Branch || Slices issue VSU & AGEN || VSU Pipe || LSU Slices
  14 KB (1,905 words) - 23:38, 22 May 2020

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