• mips/mips32 instruction set
  {{mips title|MIPS32 Instruction Set}} |design = RISC
  18 KB (2,445 words) - 08:24, 9 November 2019
• microprocessor
  ...rocessors]] (ISPs), meaning they operate on a predefined [[instruction set|set of instructions]]. In the broadest sense, their basic functionality is to c ...itecture]] (ISA) and is encoded in that instruction set. The [[instruction set architecture]] is the specification of a microprocessor design while the re
  8 KB (1,149 words) - 00:41, 16 September 2019
• ambric/am2000
  ...ell with the underlying processor that relatively easy to code. A complete set of development tools were also offered with the product including extension [[File:ambric sr core instruction.png|right]]
  11 KB (1,421 words) - 14:45, 9 December 2018
• amd/microarchitectures/zen
  |l1i desc=4-way set associative |l1d desc=8-way set associative
  79 KB (12,095 words) - 15:27, 9 June 2023
• acorn/microarchitectures/arm1
  ...in the form of evaluation systems. At that time the ARM1 was the simplest RISC processor produced. ...on the {{arm|ARMv1}} [[ISA]] which is an entirely clean-sheet {{arch|32}} RISC design.
  12 KB (1,886 words) - 12:56, 14 January 2021
• macro-operation fusion
  ...combine multiple adjacent instructions into a single instruction. A fused instruction typically remains fused throughout its lifetime. Therefore fused instructio == RISC-V ==
  11 KB (1,614 words) - 23:01, 8 May 2020
• alpha
  '''Alpha AXP''' or simply '''Alpha''' is a {{arch|64}} [[RISC]] [[instruction set architecture]] designed by [[DEC]] and introduced in [[1992]]. ...ongevity. Longevity was particularly important for DEC which is why it was set at at least 25 years. DEC went as far as to label Alpha as "The first 21st-
  755 bytes (105 words) - 13:51, 15 July 2018
• arm/armv1
  '''ARMv1''' is the first [[ARM]] instruction set version. Introduced with the {{acorn|ARM1}} on April 26 1985, the ARMv1 def ...of complex ones borrowed from early {{arch|8}} CISC microprocessors. Each instruction is 32-bit in size and operates on two 32-bit operands. There is a 24-bit [[
  10 KB (1,558 words) - 15:07, 2 July 2017
• acorn
  ...n's semiconductor business was spun off as [[ARM Holdings]] (then Advanced RISC Machines Ltd) in 1990.
  1 KB (159 words) - 17:55, 30 June 2017
• power
  ...is a [[RISC]], [[bi-endian]] (traditionally [[big-endian]]) [[instruction set architecture]]. The architecture was developed by [[IBM]] and has some use ...90 with the original (POWER1) architecture. It was originally known as the RISC System/6000 architecture.
  1 KB (133 words) - 07:30, 21 July 2018
• nudt/matrix-2000
  ...of high-performance accelerators to China. The Matrix-2000 features 128 [[RISC]] cores operating at 1.2 GHz achieving 2.46 / 4.92 [[TFLOPS]] (DP/SP) with ...to 12 stages. The core incorporates an extended 256-bit vector instruction set architecture along with two 256-bit [[vector processing units]] (VPU). Each
  6 KB (894 words) - 07:26, 19 July 2019
• sifive
  ...or company specializing in the development of the [[RISC-V]] [[Instruction Set Architecture]] and [[IP cores]]. ...e: https://chipsandcheese.com/2023/09/03/hot-chips-2023-sifives-p870-takes-risc-v-further/ -->
  1 KB (133 words) - 13:12, 4 September 2023
• pezy/pezy-scx
  ...rocessing elements''' ('''PE'''). The PEs are designed to be very simple [[RISC]] cores that are confgured as [[MIMD]] although in principle each PE can ru ...tecture implemented is a proprietary one designed by PEZY. The instruction set supports various operations such as data flashing, synchronization, acquisi
  6 KB (838 words) - 09:33, 9 May 2019
• risc-v
  {{title|RISC-V}}{{risc-v isa main}} ...fically designed to enable configurability, modularity, and extensibility. RISC-V is not designed to replace prominent ISAs such as [[x86]] and [[ARM]], bu
  3 KB (413 words) - 12:00, 25 December 2017
• risc-v/foundation
  {{risc-v title|Foundation}}{{risc-v isa main}} ...consortium established to standardize and promote the [[RISC-V]] ISA. The RISC-V foundation is a 501(C)(6) organization established on July 31, 2015.
  854 bytes (113 words) - 04:01, 11 December 2017
• risc-v/standard extensions
  {{risc-v title|Standard Extensions}}{{risc-v isa main}} RISC-V has standardized a series of '''standard extensions''' beyond the integer
  3 KB (363 words) - 12:04, 30 May 2023
• risc-v/registers
  {{risc-v title|Registers}}{{risc-v isa main}} RISC-V defines a set of '''registers''' that are part of the core ISA.
  3 KB (424 words) - 09:03, 1 March 2022
• zero register
  ...ound in many [[RISC]] instruction set architectures such as [[MIPS]] and [[RISC-V]]. On those architectures writing to that register is always discarded an
  544 bytes (78 words) - 03:04, 12 December 2017
• greenwaves/gap8
  |isa family=RISC-V ...sed on the {{ethz|PULP}} open core. The GAP8 incorporates [[9 cores|nine]] RISC-V cores capable of running at up to 250 MHz along with a [[neural processor
  6 KB (981 words) - 14:11, 28 February 2018
• movidius/microarchitectures/shave v2.0
  |l2 desc=2-way set associative * Hybrid [[RISC]]-[[DSP]]-[[GPU]] [[VLIW]] architecture
  12 KB (1,749 words) - 19:05, 20 January 2021

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