From WikiChip
Search results
- ** DTLB ...GUs). For data, there is 24 [[KiB]] [[write-back]] L1 cache with a 2-level DTLB hierarchy, hardware page walker, and an integer store-to-load forwarding su38 KB (5,468 words) - 20:29, 23 May 2019
- * DTLB table size doubled (128 entries -> 256 entries)5 KB (568 words) - 19:40, 30 November 2017
- ** DTLB14 KB (1,891 words) - 14:37, 6 January 2022
- ** DTLB27 KB (3,750 words) - 06:57, 18 November 2023
- *** Proper support for 1 GiB pages with 4-entry 1 GiB page DTLB (from 0) ...icated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB).84 KB (13,075 words) - 00:54, 29 December 2020
- ...icated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB). ** DTLB79 KB (11,922 words) - 06:46, 11 November 2022
- ...icated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB). ** DTLB38 KB (5,431 words) - 10:41, 8 April 2024
- ...icated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB). ** DTLB30 KB (4,192 words) - 13:48, 10 December 2023
- ** DTLB6 KB (923 words) - 16:48, 3 March 2022
- ** DTLB ...ode, and cache (including the µOP cache). The load queue, [[ITLB]], and [[DTLB]] (shaded in dark cyan) are also competitively shared but require SMT taggi79 KB (12,095 words) - 15:27, 9 June 2023
- *** 1.33 larger L2 DTLB (2048-entry, up from 1536) * DTLB57 KB (8,701 words) - 22:11, 9 October 2022
- ** DTLB6 KB (822 words) - 13:01, 19 May 2021
- * DTLB15 KB (1,978 words) - 22:13, 6 April 2023
- ** DTLB5 KB (738 words) - 13:49, 15 July 2018
- ** DTLB4 KB (527 words) - 02:09, 4 August 2017
- ...icated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB). ** DTLB52 KB (7,651 words) - 00:59, 6 July 2022
- ** DTLB11 KB (1,613 words) - 08:39, 3 March 2024
- ...icated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB). ** DTLB32 KB (4,535 words) - 05:44, 9 October 2022
- ...icated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB). ** DTLB13 KB (1,962 words) - 14:48, 21 February 2019
- ...icated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB). ** DTLB3 KB (456 words) - 14:50, 21 February 2019