Edit Values | |
Snapdragon 850 | |
General Info | |
Designer | Qualcomm |
Manufacturer | Samsung |
Model Number | SDM850 |
Market | Mobile |
Introduction | June 5, 2018 (announced) June 5, 2018 (launched) |
General Specs | |
Family | Snapdragon 800 |
Frequency | 2,960 MHz |
Microarchitecture | |
ISA | ARMv8 (ARM) |
Microarchitecture | Cortex-A75, Cortex-A55 |
Core Name | Kryo 385 Gold, Kryo 385 Silver |
Process | 10 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 8 |
Threads | 8 |
Max Memory | 8 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Snapdragon 850 is a high-performance 64-bit ARM LTE system on a chip designed by Qualcomm and introduced in mid-2018. Fabricated on Samsung's 10nm LPP process, the 850 features four Kryo 385 Silver high-efficiency cores operating at ? GHz along with four high-performance Kryo 385 Gold operating at 2.96 GHz. The Snapdragon 850 integrates the Adreno 630 GPU operation at ? MHz and features an X20 LTE modem supporting Cat 13 uplink and Cat 18 downlink. This chip supports up to 8 GiB of quad-channel LPDDR4X-3733 memory.
Contents
Overview[edit]
Positioned as a replacement for the 845 for always-connected ARM-based PCs and fabricated on Samsung's second-generation 10LPP process, the 850 is for the most part a higher-binned version of its predecessor. The chip features four high-performance cores based on the Cortex-A75 microarchitecture and four low-power cores based on the Cortex-A55 microarchitecture. This chip incorporates the X20 LTE modem, supporting Cat 18 up to 1.2 Gbps download and Cat 13 up to 150 Mbps upload.
Cache[edit]
- Main articles: Cortex-A75 § Cache and Cortex-A55 § Cache
Quad-core cluster Cortex-A75:
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Quad-core cluster Cortex-A55:
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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- 2 MiB L3
Memory controller[edit]
Integrated Memory Controller
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DSP[edit]
This chip features Qualcomm's Hexagon 685 DSP.
Graphics[edit]
Integrated Graphics Information
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- Hardware Acceleration
- 4K HDR video playback (10-bit color depth, Rec. 2020 color gamut)
- Decode: H.264 (AVC), H.265 (HEVC) and VP9
- Up to 4K Ultra HD video capture @ 30FPS
- Up to 1080p video capture @120 FPS
Audio[edit]
- Aqstic audio codec and Aqstic smart speaker amplifier
- Up to native DSD support, PCM up to 384 kHz/32-bit
- Qualcomm aptX audio playback with support for aptX Classic and HD
ISP[edit]
- 2x Image Sensor Processor (ISP)
- 14-bit
Megapixel:
- Up to 16 MP dual camera
- Up to 32 MP single camera
Connectivity[edit]
- WiFi
- Integrated 802.11ac 2 x 2 with MU-MIMO
- Tri-band Wi-Fi: 2.4 GHz and 5 GHz with Dual
- Band Simultaneous (DBS) + 60 GHz
- Bluetooth 5.0
- RF Front End
- LTE Modem
- Snapdragon X15
- Downlink:
- Category 18 up to 1,200 Mbps
- 5 x 20 MHz carrier aggregation, up to 256-QAM
- Up to 4 x 4 MIMO on three aggregated carriers
- Uplink:
- Category 13 up to 150 Mbps
- 2 x 20 MHz carrier aggregation, up to 64-QAM
- Downlink:
- Snapdragon X15
Location[edit]
- GPS
- Glonass, BeiDou, Galileo, QZSS, and SBAS
- Low power geofencing and tracking, sensor assisted navigation
base frequency | 2,960 MHz (2.96 GHz, 2,960,000 kHz) + |
core count | 8 + |
core name | Kryo 385 Gold + and Kryo 385 Silver + |
designer | Qualcomm + |
dsp | Hexagon 685 DSP + |
family | Snapdragon 800 + |
first announced | June 5, 2018 + |
first launched | June 5, 2018 + |
full page name | qualcomm/snapdragon 800/850 + |
has ecc memory support | false + |
instance of | microprocessor + |
integrated gpu | Adreno 630 + |
integrated gpu designer | Qualcomm + |
isa | ARMv8 + |
isa family | ARM + |
l1$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1d$ description | 4-way set associative + |
l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1i$ description | 4-way set associative + and 2-way set associative + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + and 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
ldate | June 5, 2018 + |
manufacturer | Samsung + |
market segment | Mobile + |
max cpu count | 1 + |
max memory | 8,192 MiB (8,388,608 KiB, 8,589,934,592 B, 8 GiB, 0.00781 TiB) + |
max memory bandwidth | 29.87 GiB/s (30,586.88 MiB/s, 32.073 GB/s, 32,072.668 MB/s, 0.0292 TiB/s, 0.0321 TB/s) + |
max memory channels | 4 + |
microarchitecture | Cortex-A75 + and Cortex-A55 + |
model number | SDM850 + |
name | Snapdragon 850 + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |
smp max ways | 1 + |
supported memory type | LPDDR4X-3733 + |
technology | CMOS + |
thread count | 8 + |
word size | 64 bit (8 octets, 16 nibbles) + |