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K3V2 - HiSilicon
Edit Values | |||||||||
K3V2 | |||||||||
General Info | |||||||||
Designer | HiSilicon, ARM Holdings | ||||||||
Manufacturer | TSMC | ||||||||
Model Number | K3V2 | ||||||||
Part Number | Hi3620 | ||||||||
Market | Mobile | ||||||||
Introduction | February 26, 2012 (announced) February 26, 2012 (launched) | ||||||||
General Specs | |||||||||
Family | K3 | ||||||||
Frequency | 1,500 MHz | ||||||||
Microarchitecture | |||||||||
ISA | ARMv7 (ARM) | ||||||||
Microarchitecture | Cortex-A9 | ||||||||
Core Name | Cortex-A9 | ||||||||
Process | 40 nm | ||||||||
Transistors | 600,000,000 | ||||||||
Technology | CMOS | ||||||||
Word Size | 32 bit | ||||||||
Cores | 4 | ||||||||
Threads | 4 | ||||||||
Multiprocessing | |||||||||
Max SMP | 1-Way (Uniprocessor) | ||||||||
Packaging | |||||||||
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K3V2 is a 32-bit quad-core mobile ARM microprocessor introduced by HiSilicon in early 2012. This chip, which is fabricated on a 40 nm process, incorporates four Cortex-A9 cores operating at 1.5 GHz. The K3V2 integrated Vivante's GC4000 (16 cores) IGP and supports up to 2 channels of LPDDR2-900 memory.
Cache[edit]
- Main article: Cortex-A9 § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Graphics[edit]
Integrated Graphics Information
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Expansions[edit]
- 4x high-speed UART interfaces
- 2x SPI
- 2x I2C + 2x I2C for camera
- USB 2.0 On-The-Go (HS OTG) PHY
- USB 1.1
- 2x MMC/SD/SDIO interface
- 22x GPIOs
- 10 Timers
Block Diagram[edit]
Utilizing devices[edit]
- Huawei Ascend D1 Quad XL (T9510E)
- Huawei Ascend D2 (D2‐6114 HW‐03E/U9701L)
- Huawei Ascend G330D (U8825D)
- Huawei Ascend G350 (G350‐U00)
- Huawei Ascend G700 (G700‐U00)
- Huawei Ascend G716 (G716‐L070)
- Huawei Ascend Mate 2 (TD‐LTE MT2‐L05)
- Huawei Ascend P1 (P1 LTE U9202L‐2)
- Huawei Ascend P2 (P6011)
- Huawei Ascend P6 (P6‐U06)
- Huawei Ascend P6S
- Huawei Ascend W1 (W1‐U00)
- Huawei Ascend Y201
- Huawei Ascend Y300
- Huawei Honor 2 (U9508)
- Huawei Honor 3
- Huawei Honor + (T8950)
- Huawei MediaPad 10 FHD (LTE S10‐101L)
- Huawei MediaPad 10 Link (3G S10‐201u, 3G S10‐202u, LTE‐A S10‐201L)
- Huawei MediaPad 7 Lite (S7‐931u)
- Huawei MediaPad 7 Vogue
- Huawei MediaPad 7 Youth (S7‐702u)
- Huawei STREAM X GL07S
- Lexand A802
- Huawei MediaQ M310
This list is incomplete; you can help by expanding it.
Facts about "K3V2 - HiSilicon"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | K3V2 - HiSilicon#package + |
base frequency | 1,500 MHz (1.5 GHz, 1,500,000 kHz) + |
core count | 4 + |
core name | Cortex-A9 + |
designer | HiSilicon + and ARM Holdings + |
family | K3 + |
first announced | February 26, 2012 + |
first launched | February 26, 2012 + |
full page name | hisilicon/k3/k3v2 + |
has ecc memory support | false + |
instance of | microprocessor + |
integrated gpu | GC4000 + |
integrated gpu base frequency | 480 MHz (0.48 GHz, 480,000 KHz) + |
integrated gpu designer | Vivante + |
integrated gpu execution units | 16 + |
isa | ARMv7 + |
isa family | ARM + |
l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1d$ description | 4-way set associative + |
l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
ldate | February 26, 2012 + |
main image | + |
manufacturer | TSMC + |
market segment | Mobile + |
max cpu count | 1 + |
max memory bandwidth | 6.71 GiB/s (6,871.04 MiB/s, 7.205 GB/s, 7,204.808 MB/s, 0.00655 TiB/s, 0.0072 TB/s) + |
max memory channels | 2 + |
microarchitecture | Cortex-A9 + |
model number | K3V2 + |
name | K3V2 + |
package | TFBGA-576 + |
part number | Hi3620 + |
process | 40 nm (0.04 μm, 4.0e-5 mm) + |
smp max ways | 1 + |
supported memory type | LPDDR2-900 + |
technology | CMOS + |
thread count | 4 + |
transistor count | 600,000,000 + |
used by | Huawei Ascend D1 Quad XL +, Huawei Ascend D2 +, Huawei Ascend G330D +, Huawei Ascend G350 +, Huawei Ascend G700 +, Huawei Ascend G716 +, Huawei Ascend Mate 2 +, Huawei Ascend P1 +, Huawei Ascend P2 +, Huawei Ascend P6 +, Huawei Ascend P6S +, Huawei Ascend W1 +, Huawei Ascend Y201 +, Huawei Ascend Y300 +, Huawei Honor 2 +, Huawei Honor 3 +, Huawei Honor + +, Huawei MediaPad 10 FHD +, Huawei MediaPad 10 Link +, Huawei MediaPad 7 Lite +, Huawei MediaPad 7 Vogue +, Huawei MediaPad 7 Youth +, Huawei STREAM X GL07S +, Lexand A802 + and Huawei MediaQ M310 + |
word size | 32 bit (4 octets, 8 nibbles) + |