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Xeon Gold 5215M
General Info
Designer	Intel
Manufacturer	Intel
Model Number	5215M
Part Number	CD8069504214102
S-Spec	SRFBD QRGA (QS)
Market	Server
Introduction	April 2, 2019 (announced) April 2, 2019 (launched)
Release Price	$4,224.00 (tray)
Shop	Amazon
General Specs
Family	Xeon Gold
Series	5200
Locked	Yes
Frequency	2,500 MHz
Turbo Frequency	3,400 MHz (1 core)
Bus type	DMI 3.0
Bus rate	4 × 8 GT/s
Clock multiplier	25
CPUID	0x50655
Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Cascade Lake
Platform	Purley
Chipset	Lewisburg
Core Name	Cascade Lake SP
Core Family	6
Core Stepping	L0, L1
Process	14 nm
Technology	CMOS
Word Size	64 bit
Cores	10
Threads	20
Max Memory	2 TiB
Multiprocessing
Max SMP	4-Way (Multiprocessor)
Interconnect	UPI
Interconnect Links	3
Interconnect Rate	10.4 GT/s
Electrical
TDP	85 W
Packaging
Package	FCLGA-3647 (FCLGA)
Dimension	76.16 mm × 56.6 mm
Pitch	0.8585 mm × 0.9906 mm
Contacts	3647
Socket	Socket P, LGA-3647

Xeon Gold 5215M is a 64-bit deca-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 5215M is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports one AVX-512 FMA units as well as two UPI links. This microprocessor supports up 2 TiB of hexa-channel DDR4-2666 memory, operates at 2.2 GHz with a TDP of 125 W and features a turbo boost frequency of up to 3.9 GHz.

As indicated by the "M" suffix, this model features large memory support of up to 2 TiB of memory.

Cache

Main article: Cascade Lake § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 640 KiB 655,360 B 0.625 MiB L1I$ 320 KiB 327,680 B 0.313 MiB 10x32 KiB 8-way set associative   L1D$ 320 KiB 327,680 B 0.313 MiB 10x32 KiB 8-way set associative write-back L2$ 10 MiB 10,240 KiB 10,485,760 B 0.00977 GiB     10x1 MiB 16-way set associative write-back L3$ 13.75 MiB 14,080 KiB 14,417,920 B 0.0134 GiB     10x1.375 MiB 11-way set associative write-back

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR4-2666 Supports ECC Yes Max Mem 2 TiB Controllers 2 Channels 6 Max Bandwidth 119.21 GiB/s 122,071.04 MiB/s 128.001 GB/s 128,000.763 MB/s 0.116 TiB/s 0.128 TB/s Bandwidth Single 19.87 GiB/s Double 39.74 GiB/s Quad 79.47 GiB/s Hexa 119.21 GiB/s

Expansions

[Edit/Modify Expansions Info]

	Expansion Options
PCIe Revision: 3.0 Max Lanes: 48 Configuration: 1x16, x8, x4

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX MMX Extension EMMX Extended MMX Extension SSE Streaming SIMD Extensions SSE2 Streaming SIMD Extensions 2 SSE3 Streaming SIMD Extensions 3 SSSE3 Supplemental SSE3 SSE4.1 Streaming SIMD Extensions 4.1 SSE4.2 Streaming SIMD Extensions 4.2 AVX Advanced Vector Extensions AVX2 Advanced Vector Extensions 2 AVX-512 Advanced Vector 512-bit AVX512F AVX-512 Foundation AVX512CD AVX-512 Conflict Detection AVX512BW AVX-512 Byte and Word AVX512DQ AVX-512 Doubleword and Quadword Instructions AVX512VL AVX-512 Vector Length AVX512_VNNI AVX-512 Vector Neural Network Instructions ABM Advanced Bit Manipulation BMI1 Bit Manipulation Instruction Set 1 BMI2 Bit Manipulation Instruction Set 2 FMA3 3-Operand Fused-Multiply-Add AES AES Encryption Instructions RdRand Hardware RNG ADX Multi-Precision Add-Carry CLMUL Carry-less Multiplication Extension F16C 16-bit Floating Point Conversion x86-16 16-bit x86 x86-32 32-bit x86 x86-64 64-bit x86 Real Real Mode Protected Protected Mode SMM System Management Mode FPU Integrated x87 FPU NX No-eXecute HT Hyper-Threading TBT 2.0 Turbo Boost Technology 2.0 EIST Enhanced SpeedStep Technology SST Speed Shift Technology TXT Trusted Execution Technology (SMX) vPro Intel vPro VT-x VT-x (Virtualization) VT-d VT-d (I/O MMU virtualization) EPT Extended Page Tables (SLAT) TSX Transactional Synchronization Extensions VMD Volume Management Device NM Node Manager KPT Key Protection Technology PTT Platform Trust Technology MBE Ctrl Mode-Based Execute Control DL Boost Deep Learning Boost

Frequencies

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

Mode	Base	Turbo Frequency/Active Cores
		1	2	3	4	5	6	7	8	9	10
Normal	2,500MHz	3,400MHz	3,400MHz	3,200MHz	3,200MHz	3,100MHz	3,100MHz	3,100MHz	3,100MHz	3,000MHz	3,000MHz
AVX2	2,000MHz	3,100MHz	3,100MHz	2,900MHz	2,900MHz	2,800MHz	2,800MHz	2,800MHz	2,800MHz	2,600MHz	2,600MHz
AVX512	1,400MHz	2,900MHz	2,900MHz	2,500MHz	2,500MHz	1,900MHz	1,900MHz	1,900MHz	1,900MHz	1,800MHz	1,800MHz