EPYC 7261 - AMD

	Edit Values
	EPYC 7261
	General Info
Designer	AMD
Manufacturer	GlobalFoundries
Model Number	7261
Part Number	PS7261BEV8RAF
Market	Server
Introduction	June 14, 2018 (announced); June 14, 2018 (launched)
Shop	Amazon
	General Specs
Family	EPYC
Series	7000
Locked	No
Frequency	2,500 MHz
Turbo Frequency	2,900 MHz (1 core),; 2,900 MHz (2 cores),; 2,900 MHz (3 cores),; 2,900 MHz (4 cores),; 2,900 MHz (5 cores),; 2,900 MHz (6 cores),; 2,900 MHz (7 cores),; 2,900 MHz (8 cores)
Clock multiplier	25
	Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Zen
Core Name	Naples
Core Family	23
Core Model	1
Core Stepping	B2
Process	14 nm
Transistors	19,200,000,000
Technology	CMOS
Die	213 mm²
MCP	Yes (4 dies)
Word Size	64 bit
Cores	8
Threads	16
Max Memory	2 TiB
	Multiprocessing
Max SMP	2-Way (Multiprocessor)
	Electrical
TDP	155 W, 170 W
	Packaging
Package	SP3, FCLGA-4094 (FC-OLGA)
Dimension	75.4 mm × 58.5 mm × 6.26 mm
Pitch	0.87 mm × 1 mm
Contacts	4094
Socket	SP3, LGA-4094

EPYC 7261 is a dual-socket 64-bit octa-core x86 enterprise server microprocessor introduced by AMD in mid 2018. This processor is based on the Zen microarchitecture and is manufactured on a 14 nm process. The 7261 has a base frequency of 2.5 GHz with a turbo frequency of 2.9 GHz for all cores. This chip has a TDP of 170 W and supports up to 2 TiB of octa-channel DDR4-2666 ECC memory per socket. The TDP is slightly lower at 155 W if DDR4-2400 is used instead.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache[edit]

Main article: Zen § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

768 KiB

786,432 B
0.75 MiB

L1I$	512 KiB 524,288 B 0.5 MiB	8x64 KiB	4-way set associative
L1D$	256 KiB 262,144 B 0.25 MiB	8x32 KiB	8-way set associative	write-back

L2$

4 MiB

4,096 KiB
4,194,304 B
0.00391 GiB

		8x512 KiB	8-way set associative	write-back

L3$

64 MiB

65,536 KiB
67,108,864 B
0.0625 GiB

		8x8 MiB	16-way set associative

Memory controller[edit]

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	DDR4-2666, DDR4-2400
Supports ECC	Yes
Max Mem	2 TiB
Controllers	8
Channels	8
Max Bandwidth	158.95 GiB/s 162,764.8 MiB/s 170.671 GB/s 170,671.263 MB/s 0.155 TiB/s 0.171 TB/s
Bandwidth	Single 19.89 GiB/s Double 39.72 GiB/s Quad 79.47 GiB/s Hexa 119.21 GiB/s Octa 158.95 GiB/s

In a dual-socket configuration, the maximum supported memory doubles to 4 TiB along with the maximum theoretical bandwidth of 286.2 GiB/s.

Expansions[edit]

The EPYC 7261 has 128 Gen 3 PCIe lanes.

[Edit/Modify Expansions Info]

Expansion Options

PCIe

Revision	3.0
Max Lanes	128
Configs	8x16, 32x4

Features[edit]

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX	MMX Extension
EMMX	Extended MMX Extension
SSE	Streaming SIMD Extensions
SSE2	Streaming SIMD Extensions 2
SSE3	Streaming SIMD Extensions 3
SSSE3	Supplemental SSE3
SSE4.1	Streaming SIMD Extensions 4.1
SSE4.2	Streaming SIMD Extensions 4.2
SSE4a	Streaming SIMD Extensions 4a
AVX	Advanced Vector Extensions
AVX2	Advanced Vector Extensions 2
ABM	Advanced Bit Manipulation
BMI1	Bit Manipulation Instruction Set 1
BMI2	Bit Manipulation Instruction Set 2
FMA3	3-Operand Fused-Multiply-Add
AES	AES Encryption Instructions
RdRand	Hardware RNG
SHA	SHA Extensions
ADX	Multi-Precision Add-Carry
CLMUL	Carry-less Multiplication Extension
F16C	16-bit Floating Point Conversion

x86-16	16-bit x86
x86-32	32-bit x86
x86-64	64-bit x86
Real	Real Mode
Protected	Protected Mode
SMM	System Management Mode
FPU	Integrated x87 FPU
NX	No-eXecute
SMT	Simultaneous Multithreading
AMD-Vi	AMD-Vi (I/O MMU virtualization)
AMD-V	AMD Virtualization
SME	Secure Memory Encryption
TSME	Transparent SME
SEV	Secure Encrypted Virtualization
SenseMI	SenseMI Technology

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	EPYC 7261 - AMD#io +
base frequency	2,500 MHz (2.5 GHz, 2,500,000 kHz) +
clock multiplier	25 +
core count	8 +
core family	23 +
core model	1 +
core name	Naples +
core stepping	B2 +
designer	AMD +
die area	213 mm² (0.33 in², 2.13 cm², 213,000,000 µm²) +
die count	4 +
family	EPYC +
first announced	June 14, 2018 +
first launched	June 14, 2018 +
full page name	amd/epyc/7261 +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has amd amd-v technology	true +
has amd amd-vi technology	true +
has amd secure encrypted virtualization technology	true +
has amd secure memory encryption technology	true +
has amd sensemi technology	true +
has amd transparent secure memory encryption technology	true +
has ecc memory support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension + and SenseMI Technology +
has locked clock multiplier	false +
has simultaneous multithreading	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
is multi-chip package	true +
isa	x86-64 +
isa family	x86 +
l1$ size	768 KiB (786,432 B, 0.75 MiB) +
l1d$ description	8-way set associative +
l1d$ size	256 KiB (262,144 B, 0.25 MiB) +
l1i$ description	4-way set associative +
l1i$ size	512 KiB (524,288 B, 0.5 MiB) +
l2$ description	8-way set associative +
l2$ size	4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ description	16-way set associative +
l3$ size	64 MiB (65,536 KiB, 67,108,864 B, 0.0625 GiB) +
ldate	June 14, 2018 +
manufacturer	GlobalFoundries +
market segment	Server +
max cpu count	2 +
max memory	2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) +
max memory bandwidth	158.95 GiB/s (162,764.8 MiB/s, 170.671 GB/s, 170,671.263 MB/s, 0.155 TiB/s, 0.171 TB/s) +
max memory channels	8 +
max pcie lanes	128 +
microarchitecture	Zen +
model number	7261 +
name	EPYC 7261 +
package	SP3 + and FCLGA-4094 +
part number	PS7261BEV8RAF +
process	14 nm (0.014 μm, 1.4e-5 mm) +
series	7000 +
smp max ways	2 +
socket	SP3 + and LGA-4094 +
supported memory type	DDR4-2666 + and DDR4-2400 +
tdp	155 W (155,000 mW, 0.208 hp, 0.155 kW) + and 170 W (170,000 mW, 0.228 hp, 0.17 kW) +
technology	CMOS +
thread count	16 +
transistor count	19,200,000,000 +
turbo frequency (1 core)	2,900 MHz (2.9 GHz, 2,900,000 kHz) +
turbo frequency (2 cores)	2,900 MHz (2.9 GHz, 2,900,000 kHz) +
turbo frequency (3 cores)	2,900 MHz (2.9 GHz, 2,900,000 kHz) +
turbo frequency (4 cores)	2,900 MHz (2.9 GHz, 2,900,000 kHz) +
turbo frequency (5 cores)	2,900 MHz (2.9 GHz, 2,900,000 kHz) +
turbo frequency (6 cores)	2,900 MHz (2.9 GHz, 2,900,000 kHz) +
turbo frequency (7 cores)	2,900 MHz (2.9 GHz, 2,900,000 kHz) +
turbo frequency (8 cores)	2,900 MHz (2.9 GHz, 2,900,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +

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Contents

Cache[edit]

Memory controller[edit]

Expansions[edit]

Features[edit]