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Difference between revisions of "sifive/microarchitectures/7 series"
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(7 series)
 
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{{sifive title|7 Series|arch}}
 
{{sifive title|7 Series|arch}}
−
{{microarchitecture}}
+
{{microarchitecture
 +
|atype=CPU
 +
|name=7 Series
 +
|designer=SiFive
 +
|manufacturer=TSMC
 +
|manufacturer 2=GlobalFoundries
 +
|introduction=October 21, 2018
 +
|cores=1
 +
|cores 2=2
 +
|cores 3=4
 +
|cores 4=6
 +
|cores 5=8
 +
|type=Superscalar
 +
|type 2=Pipelined
 +
|oooe=No
 +
|speculative=Yes
 +
|renaming=No
 +
|stages=8
 +
|decode=2
 +
|isa=RISC-V
 +
|feature=RV32IMAFDCV
 +
|feature 2=RV64IMAFDCV
 +
|core name=E76
 +
|core name 2=E76-MC
 +
|core name 3=S76
 +
|core name 4=S76-MC
 +
|core name 5=U74
 +
|core name 6=U74-MC
 +
|predecessor=5 Series
 +
|predecessor link=sifive/microarchitectures/5_series
 +
}}
 
'''7 Series''' is a series of high-performance [[RISC-V]] [[IP cores]] designed by [[SiFive]].
 
'''7 Series''' is a series of high-performance [[RISC-V]] [[IP cores]] designed by [[SiFive]].

Revision as of 21:00, 4 November 2018

Edit Values
7 Series µarch
General Info
Arch TypeCPU
DesignerSiFive
ManufacturerTSMC, GlobalFoundries
IntroductionOctober 21, 2018
Core Configs1, 2, 4, 6, 8
Pipeline
TypeSuperscalar, Pipelined
OoOENo
SpeculativeYes
Reg RenamingNo
Stages8
Decode2
Instructions
ISARISC-V
Cores
Core NamesE76,
E76-MC,
S76,
S76-MC,
U74,
U74-MC
Succession

7 Series is a series of high-performance RISC-V IP cores designed by SiFive.

Retrieved from "https://en.wikichip.org/w/index.php?title=sifive/microarchitectures/7_series&oldid=83851"
Facts about "7 Series - Microarchitectures - SiFive"
RDF feed
codename7 Series +
core count1 +, 2 +, 4 +, 6 + and 8 +
designerSiFive +
first launchedOctober 21, 2018 +
full page namesifive/microarchitectures/7 series +
instance ofmicroarchitecture +
instruction set architectureRISC-V +
manufacturerTSMC + and GlobalFoundries +
microarchitecture typeCPU +
name7 Series +
pipeline stages8 +