Difference between revisions of "risc-v/microarchitectures"

Revision as of 01:15, 29 July 2019

RISC-V
Instruction Set Architecture

v · d · e

Various microarchitectures have been designed for RISC-V by a number of companies. Below is a list of those microarchitectures.

@@ Line 6: / Line 6: @@
 ! Designer !! ISA !! Microarchitectures
 |-
-| rowspan="4" | [[SiFive]] || RV32IMAC || {{sifive|E31|l=arch}}
+| [[Andes]] || RV32IMAC || {{andes|N25|l=arch}}
 |-
-| RV64IMAC || {{sifive|E51|l=arch}}
+| rowspan="3" | [[Codasip]] || RV32E || {{codasip|CODIX-BK1|l=arch}}
 |-
-| RV64GC || {{sifive|E54-MC|l=arch}}
+| RV32[E,I] || {{codasip|CODIX-BK3|l=arch}}
 |-
-| RV[32,64]IMAFDCV || {{sifive|7 Series|l=arch}}
+| RV[32,64]I || {{codasip|CODIX-BK5|l=arch}}
-|-
-| [[Andes]] || RV32IMAC || {{andes|N25|l=arch}}
 |-
 | [[Esperanto]] || RV64GC || {{esperanto|ET-Minion|l=arch}}, {{esperanto|ET-Maxion|l=arch}}
@@ Line 24: / Line 22: @@
 | [[Nvidia]] || RV64I || {{nvidia|NV-RISCV|l=arch}}
 |-
-| rowspan="3" | [[Codasip]] || RV32E || {{codasip|CODIX-BK1|l=arch}}
+| rowspan="4" | [[SiFive]] || RV32IMAC || {{sifive|E31|l=arch}}
+|-
+| RV64IMAC || {{sifive|E51|l=arch}}
+|-
+| RV64GC || {{sifive|E54-MC|l=arch}}
+|-
+| RV[32,64]IMAFDCV || {{sifive|7 Series|l=arch}}
 |-
-| RV32[E,I] || {{codasip|CODIX-BK3|l=arch}}
+| rowspan="2" | [[T-Head]] || {{t-head|C910}} || RV64GC[V,RV]
 |-
-| RV[32,64]I || {{codasip|CODIX-BK5|l=arch}}
+| {{t-head|E902}} || RV32[EMC,EC,IMC]
 |}