Revision history of "nvidia/tegra/xavier"

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(cur | prev) 09:04, 17 March 2025‎ 213.247.143.23 (talk)‎ . . (8,696 bytes) (+36)‎ . . (→‎Deep Learning Accelerator: Add link to Nvidia NVDLA architecture) (undo)
(cur | prev) 02:08, 9 December 2019‎ 199.116.118.167 (talk)‎ . . (8,660 bytes) (+2)‎ . . (→‎GPU: Fixed tensor core MACs per cycle numbers.) (undo)
(cur | prev) 20:50, 26 April 2019‎ David (talk | contribs)‎ . . (8,658 bytes) (+46)‎ . . (undo)
(cur | prev) 10:23, 17 December 2018‎ 141.113.3.11 (talk)‎ . . (8,612 bytes) (+1)‎ . . (→‎Deep Learning Accelerator) (undo)
(cur | prev) 22:09, 4 November 2018‎ 72.31.25.172 (talk)‎ . . (8,611 bytes) (-143)‎ . . (Corrected errors based on latest NVIDIA specs) (undo)
(cur | prev) 09:42, 29 September 2018‎ David (talk | contribs)‎ m . . (8,754 bytes) (+2)‎ . . (→‎GPU) (undo)
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(cur | prev) 06:11, 14 September 2018‎ 4.14.180.238 (talk)‎ . . (8,740 bytes) (+1)‎ . . (earning->learning) (undo)
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(cur | prev) 21:13, 2 September 2018‎ David (talk | contribs)‎ . . (7,521 bytes) (+1,148)‎ . . (→‎Architecture) (undo)
(cur | prev) 20:55, 2 September 2018‎ David (talk | contribs)‎ . . (6,373 bytes) (+270)‎ . . (→‎Overview) (undo)
(cur | prev) 20:52, 2 September 2018‎ David (talk | contribs)‎ . . (6,103 bytes) (+590)‎ . . (→‎Architecture) (undo)
(cur | prev) 20:45, 2 September 2018‎ David (talk | contribs)‎ . . (5,513 bytes) (0)‎ . . (→‎GPU) (undo)
(cur | prev) 20:45, 2 September 2018‎ David (talk | contribs)‎ . . (5,513 bytes) (+431)‎ . . (→‎GPU) (undo)
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(cur | prev) 14:25, 2 September 2018‎ David (talk | contribs)‎ . . (4,820 bytes) (+176)‎ . . (undo)
(cur | prev) 12:41, 2 September 2018‎ David (talk | contribs)‎ . . (4,644 bytes) (0)‎ . . (→‎MM Engine / DLA) (undo)
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(cur | prev) 12:56, 29 August 2018‎ David (talk | contribs)‎ m . . (3,692 bytes) (0)‎ . . (David moved page nvidia/drive/xavier to nvidia/tegra/xavier: part of tegra) (undo)
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core count	8 +
core name	Carmel +
designer	Nvidia +
die area	350 mm² (0.543 in², 3.5 cm², 350,000,000 µm²) +
family	Tegra +
first announced	January 8, 2018 +
first launched	June 2018 +
full page name	nvidia/tegra/xavier +
has ecc memory support	true +
instance of	microprocessor +
isa	ARMv8 +
isa family	ARM +
ldate	June 2018 +
main image	+
manufacturer	TSMC +
market segment	Artificial Intelligence + and Embedded +
max cpu count	4 +
max memory bandwidth	127.1 GiB/s (130,150.4 MiB/s, 136.473 GB/s, 136,472.586 MB/s, 0.124 TiB/s, 0.136 TB/s) +
max memory channels	8 +
microarchitecture	Carmel + and Volta +
model number	Tegra194 +
name	Xavier +
process	12 nm (0.012 μm, 1.2e-5 mm) +
smp max ways	4 +
supported memory type	LPDDR4X-4266 +
tdp	30 W (30,000 mW, 0.0402 hp, 0.03 kW) +
tdp (typical)	20 W (20,000 mW, 0.0268 hp, 0.02 kW) +
technology	CMOS +
thread count	8 +
transistor count	9,000,000,000 +
word size	64 bit (8 octets, 16 nibbles) +

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