Semiconductor & Computer Engineering
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Information for "nvidia/tegra/xavier"
Basic information
| Display title | Tegra Xavier - Nvidia |
| Default sort key | Tegra Xavier, Nvidia |
| Page length (in bytes) | 8,660 |
| Page ID | 27672 |
| Page content language | English (en) |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 12 |
| Counted as a content page | Yes |
| Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | David (talk | contribs) |
| Date of page creation | 23:15, 9 January 2018 |
| Latest editor | 199.116.118.167 (talk) |
| Date of latest edit | 03:08, 9 December 2019 |
| Total number of edits | 59 |
| Total number of distinct authors | 6 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
Page properties
| Transcluded templates (16) | Templates used on this page:
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Facts about "Tegra Xavier - Nvidia"
| core count | 8 + |
| designer | Nvidia + |
| die area | 350 mm² (0.543 in², 3.5 cm², 350,000,000 µm²) + |
| family | Tegra + |
| first announced | January 8, 2018 + |
| full page name | nvidia/tegra/xavier + |
| has ecc memory support | true + |
| instance of | microprocessor + |
| isa | ARMv8 + |
| isa family | ARM + |
| ldate | 3000 + |
| manufacturer | TSMC + |
| market segment | Artificial Intelligence + |
| max memory bandwidth | 127.1 GiB/s (130,150.4 MiB/s, 136.473 GB/s, 136,472.586 MB/s, 0.124 TiB/s, 0.136 TB/s) + |
| max memory channels | 8 + |
| name | Xavier + |
| process | 12 nm (0.012 μm, 1.2e-5 mm) + |
| supported memory type | LPDDR4-2133 + |
| tdp | 30 W (30,000 mW, 0.0402 hp, 0.03 kW) + |
| tdp (typical) | 20 W (20,000 mW, 0.0268 hp, 0.02 kW) + |
| technology | CMOS + |
| thread count | 8 + |
| transistor count | 9,000,000,000 + |
| word size | 64 bit (8 octets, 16 nibbles) + |