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Information for "nervana/microarchitectures/lake crest"
Basic information
Display title | Lake Crest - Microarchitectures - Intel Nervana |
Default sort key | Lake Crest, Nervana |
Page length (in bytes) | 1,752 |
Page ID | 27491 |
Page content language | English (en) |
Page content model | wikitext |
Indexing by robots | Allowed |
Number of redirects to this page | 2 |
Counted as a content page | Yes |
Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
Edit | Allow all users (infinite) |
Move | Allow all users (infinite) |
Edit history
Page creator | David (talk | contribs) |
Date of page creation | 01:50, 29 December 2017 |
Latest editor | David (talk | contribs) |
Date of latest edit | 16:51, 6 August 2020 |
Total number of edits | 16 |
Total number of distinct authors | 4 |
Recent number of edits (within past 90 days) | 0 |
Recent number of distinct authors | 0 |
Page properties
Transcluded templates (6) | Templates used on this page: |
Facts about "Lake Crest - Microarchitectures - Intel Nervana"
codename | Lake Crest + |
designer | Nervana + |
first launched | November 17, 2016 + |
full page name | nervana/microarchitectures/lake crest + |
instance of | microarchitecture + |
manufacturer | TSMC + |
name | Lake Crest + |
process | 28 nm (0.028 μm, 2.8e-5 mm) + |