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Difference between revisions of "movidius/microarchitectures/shave v2.0"
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| − | {{movidius title|SHAVE}} | + | {{movidius title|SHAVE v2.0|arch}} |
{{microarchitecture | {{microarchitecture | ||
| − | |atype= | + | |atype=Accelerator |
| − | |name=SHAVE | + | |name=SHAVE v2.0 |
|designer=Movidius | |designer=Movidius | ||
|manufacturer=TSMC | |manufacturer=TSMC | ||
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|type=VLIW | |type=VLIW | ||
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| − | '''Streaming Hybrid Architecture Vector Engine''' ('''SHAVE''') is | + | '''Streaming Hybrid Architecture Vector Engine v2.0''' ('''SHAVE v2.0''') is an accelerator microarchitecture designed by [[Movidius]] for their vision processors. SHAVE is incorporated into Movidius {{movidius|Myriad}} family of vision processors. |
== Architecture == | == Architecture == | ||
Revision as of 16:31, 10 March 2018
| Edit Values | |
| SHAVE v2.0 µarch | |
| General Info | |
| Arch Type | Accelerator |
| Designer | Movidius |
| Manufacturer | TSMC |
| Introduction | 2011 |
| Pipeline | |
| Type | VLIW |
Streaming Hybrid Architecture Vector Engine v2.0 (SHAVE v2.0) is an accelerator microarchitecture designed by Movidius for their vision processors. SHAVE is incorporated into Movidius Myriad family of vision processors.
Architecture
- Hybrid RISC-DSP-GPU VLIW architecture
- Predicated execution
- Branch delay slots
- Tailored to streaming workloads
- 128-bit vector arithmetic
- 8/16/32-bit integer
- 16/32-bit floating point
- Full support for sparse data structures (matrix/array, random access)
Instruction Set
SHAVE supports a mixture of many different types of instructions belonging to a number of different classes of architectures.
- RISC style
- Instruction predication
- Large set of integer operations
- C-compiler support
- VLIW style
- Parallel functional units controlled by VLIW instructions
- 8/16/32-bit x 1-4 SIMD int
- DSP style
- Zero overhead looping
- Modulo addressing
- Transparent DMA modes
- FFT, Viterbi, etc..
- Parallel comparisons
- GPU style
- Streaming operations
- 16/32-bit FP operations
- Texture management unit
Facts about "SHAVE v2.0 - Microarchitectures - Intel Movidius"
| codename | SHAVE v2.0 + |
| designer | Movidius + |
| first launched | 2011 + |
| full page name | movidius/microarchitectures/shave v2.0 + |
| instance of | microarchitecture + |
| manufacturer | TSMC + |
| name | SHAVE v2.0 + |
