Difference between revisions of "intel/xeon d/d-1518"

	Edit Values
	Xeon D-1518
	General Info
Designer	Intel
Manufacturer	Intel
Model Number	D-1518
Part Number	GG8067402569700
S-Spec	SR2DN
Market	Server, Embedded
Introduction	March 9, 2015 (announced); March 9, 2015 (launched)
Release Price	$193.00 (tray)
Shop	Amazon
	General Specs
Family	Xeon D
Series	D-1500
Locked	Yes
Frequency	2,200 MHz
Bus type	DMI 2.0
Clock multiplier	22
	Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Broadwell
Platform	Grangeville
Core Name	Broadwell DE
Core Family	6
Core Model	6
Core Stepping	V2
Process	14 nm
Transistors	3,200,000,000
Technology	CMOS
Die	246.24 mm²
Word Size	64 bit
Cores	4
Threads	8
Max Memory	128 GiB
	Multiprocessing
Max SMP	1-Way (Uniprocessor)
	Electrical
TDP	35 W
OP Temperature	0 °C – 108 °C
	Packaging
Package	FCBGA-1667 (FCBGA)
Dimension	37.5 mm × 37.5 mm × 3.557 mm
Pitch	0.7 mm
Contacts	1667

Revision as of 01:01, 1 April 2019

Xeon D-1518 is a 64-bit quad-core x86 microserver SoC introduced by Intel in late 2015. The D-1518 is based on the Broadwell microarchitecture and is fabricated on their 14 nm process. It operates at 2.2 GHz with a TDP of 35 W and supports up to 128 GiB of dual-channel DDR4-2133 memory.

Cache

Main article: Broadwell § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

256 KiB

262,144 B
0.25 MiB

L1I$	128 KiB 131,072 B 0.125 MiB	4x32 KiB	8-way set associative
L1D$	128 KiB 131,072 B 0.125 MiB	4x32 KiB	8-way set associative	write-back

L2$

1 MiB

1,024 KiB
1,048,576 B
9.765625e-4 GiB

		4x256 KiB	8-way set associative	write-back

L3$

6 MiB

6,144 KiB
6,291,456 B
0.00586 GiB

		6x1.5 MiB	16-way set associative	write-back

Graphics

This SoC has no integrated graphics processing unit.

Memory controller

Integrated Memory Controller
Type	DDR3L-1333, DDR3L-1600, DDR4-1600, DDR4-1867, DDR4-2133
Controllers	1
Channels	2
ECC Support	Yes
Max memory	128 GiB

Expansions

[Edit/Modify Expansions Info]

Expansion Options

PCIe

Revision	2.0
Max Lanes	8
Configs	x4, x16

USB

Revision	2.0, 3.0
Ports	8

UART

Integrated LAN	Yes

Networking

Networking
SFI interface	Yes
KR interface	No
KX interface	Yes
KX4 interface	No
10Base-T	No
100Base-T	No
1000Base-T	Yes
10GBase-T	Yes

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX	MMX Extension
SSE	Streaming SIMD Extensions
SSE2	Streaming SIMD Extensions 2
SSE3	Streaming SIMD Extensions 3
SSSE3	Supplemental SSE3
AVX	Advanced Vector Extensions
AVX2	Advanced Vector Extensions 2
BMI1	Bit Manipulation Instruction Set 1
BMI2	Bit Manipulation Instruction Set 2
FMA3	3-Operand Fused-Multiply-Add
AES	AES Encryption Instructions
F16C	16-bit Floating Point Conversion

NX	No-eXecute
HT	Hyper-Threading
EIST	Enhanced SpeedStep Technology
TXT	Trusted Execution Technology (SMX)
VT-x	VT-x (Virtualization)
VT-d	VT-d (I/O MMU virtualization)
EPT	Extended Page Tables (SLAT)
TSX	Transactional Synchronization Extensions

@@ Line 46: / Line 46: @@
 == Cache ==
-{{main|intel/microarchitectures/broadwell#Memory_Hierarchy|l1=Broadwell § Cache}}
+{{main|intel/microarchitectures/broadwell (server)#Memory_Hierarchy|l1=Broadwell § Cache}}
-{{cache info
+{{cache size
+|l1 cache=256 KiB
 |l1i cache=128 KiB
 |l1i break=4x32 KiB
 |l1i desc=8-way set associative
-|l1i extra=(per core)
 |l1d cache=128 KiB
 |l1d break=4x32 KiB
 |l1d desc=8-way set associative
-|l1d extra=(per core)
+|l1d policy=write-back
 |l2 cache=1 MiB
 |l2 break=4x256 KiB
 |l2 desc=8-way set associative
-|l2 extra=(per core)
+|l2 policy=write-back
 |l3 cache=6 MiB
-|l3 break=4x1.5 MiB
+|l3 break=6x1.5 MiB
-|l3 extra=(per core)
+|l3 desc=16-way set associative
+|l3 policy=write-back
 }}

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon D-1518 - Intel#io +
back image	+
base frequency	2,200 MHz (2.2 GHz, 2,200,000 kHz) +
bus type	DMI 2.0 +
clock multiplier	22 +
core count	4 +
core family	6 +
core model	6 +
core name	Broadwell DE +
core stepping	V2 +
designer	Intel +
die area	246.24 mm² (0.382 in², 2.462 cm², 246,240,000 µm²) +
family	Xeon D +
first announced	March 9, 2015 +
first launched	March 9, 2015 +
full page name	intel/xeon d/d-1518 +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables + and Transactional Synchronization Extensions +
has intel enhanced speedstep technology	true +
has intel trusted execution technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	256 KiB (262,144 B, 0.25 MiB) +
l1d$ description	8-way set associative +
l1d$ size	128 KiB (131,072 B, 0.125 MiB) +
l1i$ description	8-way set associative +
l1i$ size	128 KiB (131,072 B, 0.125 MiB) +
l2$ description	8-way set associative +
l2$ size	1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ description	16-way set associative +
l3$ size	6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) +
ldate	March 9, 2015 +
main image	+
manufacturer	Intel +
market segment	Server + and Embedded +
max cpu count	1 +
max memory	131,072 MiB (134,217,728 KiB, 137,438,953,472 B, 128 GiB, 0.125 TiB) +
max operating temperature	108 °C +
max pcie lanes	8 +
microarchitecture	Broadwell +
min operating temperature	0 °C +
model number	D-1518 +
name	Xeon D-1518 +
package	FCBGA-1667 +
part number	GG8067402569700 +
platform	Grangeville +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 193.00 (€ 173.70, £ 156.33, ¥ 19,942.69) +
release price (tray)	$ 193.00 (€ 173.70, £ 156.33, ¥ 19,942.69) +
s-spec	SR2DN +
series	D-1500 +
smp max ways	1 +
tdp	35 W (35,000 mW, 0.0469 hp, 0.035 kW) +
technology	CMOS +
thread count	8 +
transistor count	3,200,000,000 +
word size	64 bit (8 octets, 16 nibbles) +

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