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Difference between revisions of "intel/microarchitectures/whiskey lake"
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Revision as of 01:44, 19 December 2017
| Edit Values | |
| Whiskey Lake µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | July, 2018 |
| Process | 14 nm |
| Core Configs | 4 |
| Pipeline | |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Stages | 14-19 |
| Decode | 5-way |
| Instructions | |
| ISA | x86-64 |
| Extensions | MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX |
| Cache | |
| L1I Cache | 32 KiB/core 8-way set associative |
| L1D Cache | 32 KiB/core 8-way set associative |
| L2 Cache | 256 KiB/core 4-way set associative |
| L3 Cache | 2 MiB/core Up to 16-way set associative |
| Cores | |
| Core Names | Whiskey Lake U |
| Succession | |
| Contemporary | |
| Cannon Lake | |
Whiskey Lake (WHL) is a microarchitecture designed by Intel as a successor to Coffee Lake for mobile devices. Whiskey Lake is expected to launch in the third quarter of 2018 and is manufactured on Intel's mature 14 nm process.
Facts about "Whiskey Lake - Microarchitectures - Intel"
| codename | Whiskey Lake + |
| core count | 4 + |
| designer | Intel + |
| first launched | July 2018 + |
| full page name | intel/microarchitectures/whiskey lake + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Whiskey Lake + |
| pipeline stages (max) | 19 + |
| pipeline stages (min) | 14 + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) + |
