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Information for "intel/microarchitectures/tiger lake"
Basic information
Display title | Tiger Lake - Microarchitectures - Intel |
Default sort key | Tiger Lake, Intel |
Page length (in bytes) | 2,962 |
Page ID | 6827 |
Page content language | English (en) |
Page content model | wikitext |
Indexing by robots | Allowed |
Number of redirects to this page | 3 |
Counted as a content page | Yes |
Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
Edit | Allow all users (infinite) |
Move | Allow all users (infinite) |
Edit history
Page creator | At32Hz (talk | contribs) |
Date of page creation | 00:34, 15 April 2016 |
Latest editor | 213.175.37.10 (talk) |
Date of latest edit | 10:46, 19 July 2023 |
Total number of edits | 48 |
Total number of distinct authors | 21 |
Recent number of edits (within past 90 days) | 0 |
Recent number of distinct authors | 0 |
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Facts about "Tiger Lake - Microarchitectures - Intel"
codename | Tiger Lake + |
core count | 2 +, 4 +, 6 + and 8 + |
designer | Intel + |
first launched | September 2, 2020 + |
full page name | intel/microarchitectures/tiger lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Tiger Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |