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Information for "intel/microarchitectures/tiger lake"

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Display titleTiger Lake - Microarchitectures - Intel
Default sort keyTiger Lake, Intel
Page length (in bytes)2,866
Page ID6827
Page content languageEnglish (en)
Page content modelwikitext
Indexing by robotsAllowed
Number of redirects to this page3
Counted as a content pageYes
Number of subpages of this page0 (0 redirects; 0 non-redirects)

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Edit history

Page creatorAt32Hz (talk | contribs)
Date of page creation00:34, 15 April 2016
Latest editor173.244.217.55 (talk)
Date of latest edit12:29, 20 June 2021
Total number of edits47
Total number of distinct authors20
Recent number of edits (within past 90 days)0
Recent number of distinct authors0

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Transcluded templates (9)

Templates used on this page:

codenameTiger Lake +
core count2 +, 4 +, 6 + and 8 +
designerIntel +
first launchedSeptember 2, 2020 +
full page nameintel/microarchitectures/tiger lake +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameTiger Lake +
pipeline stages (max)19 +
pipeline stages (min)14 +
process10 nm (0.01 μm, 1.0e-5 mm) +