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Difference between revisions of "intel/microarchitectures/netburst (client)"
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== Die ==
 
== Die ==
 +
=== Willamette ===
 
* {{intel|Willamette|l=core}} core
 
* {{intel|Willamette|l=core}} core
 
* [[180 nm process]]
 
* [[180 nm process]]
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:[[File:netburst willamette core die.png|700px]]
 
:[[File:netburst willamette core die.png|700px]]
 +
 +
=== Northwood ===
 +
* {{intel|Northwood|l=core}} core
 +
* [[130 nm process]]
 +
* 131 mm² die size
 +
* 55,000,000 transistors
 +
 +
 +
:[[File:netburst northwood core die.png|700px]]
 +
 +
 +
=== Prescott ===
 +
* {{intel|Prescott|l=core}} core
 +
* [[90 nm process]]
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* 135 mm² die size
 +
* 169,000,000 transistors
 +
 +
 +
:[[File:netburst prescott core die.png|700px]]
  
 
=== Additional Shots ===
 
=== Additional Shots ===

Revision as of 00:36, 10 April 2018

Edit Values
NetBurst µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
IntroductionNovember 20, 2000
Phase-outApril, 2006
Process180 nm
Instructions
ISAx86-32, x86-64
Succession

NetBurst (also P68) was the microarchitecture for Intel's 180 nm process for desktops and servers as a successor to P6. NetBurst was replaced by the Core microarchitecture in early 2006.

Die

Willamette


netburst willamette core die.png

Northwood


netburst northwood core die.png


Prescott


netburst prescott core die.png

Additional Shots

Additional die and wafer shots provided by Intel:

codenameNetBurst +
designerIntel +
first launchedNovember 20, 2000 +
full page nameintel/microarchitectures/netburst (client) +
instance ofmicroarchitecture +
instruction set architecturex86-32 + and x86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameNetBurst +
phase-outApril 2006 +
process180 nm (0.18 μm, 1.8e-4 mm) +