From WikiChip
Information for "intel/microarchitectures/cascade lake"

Basic information

Display titleCascade Lake - Microarchitectures - Intel
Default sort keyCascade Lake, Intel
Page length (in bytes)32,662
Page ID27157
Page content languageEnglish (en)
Page content modelwikitext
Indexing by robotsAllowed
Number of redirects to this page4
Counted as a content pageYes
Number of subpages of this page0 (0 redirects; 0 non-redirects)

Page protection

EditAllow all users (infinite)
MoveAllow all users (infinite)

Edit history

Page creatorDavid (talk | contribs)
Date of page creation09:07, 5 December 2017
Latest editorDavid (talk | contribs)
Date of latest edit00:42, 5 August 2019
Total number of edits98
Total number of distinct authors10
Recent number of edits (within past 90 days)20
Recent number of distinct authors4

Page properties

Transcluded templates (23)

Templates used on this page:

codenameCascade Lake +
core count2 +, 4 +, 6 +, 8 +, 10 +, 12 +, 16 +, 18 +, 20 +, 22 +, 24 +, 26 +, 28 +, 32 +, 48 + and 56 +
designerIntel +
first launched2019 +
full page nameintel/microarchitectures/cascade lake +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameCascade Lake +
pipeline stages (max)19 +
pipeline stages (min)14 +
process14 nm (0.014 μm, 1.4e-5 mm) +