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Information for "intel/microarchitectures/cascade lake"
Basic information
Display title | Cascade Lake - Microarchitectures - Intel |
Default sort key | Cascade Lake, Intel |
Page length (in bytes) | 32,672 |
Page ID | 27157 |
Page content language | English (en) |
Page content model | wikitext |
Indexing by robots | Allowed |
Number of redirects to this page | 4 |
Counted as a content page | Yes |
Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
Edit | Allow all users (infinite) |
Move | Allow all users (infinite) |
Edit history
Page creator | David (talk | contribs) |
Date of page creation | 09:07, 5 December 2017 |
Latest editor | 78.177.142.107 (talk) |
Date of latest edit | 12:12, 24 September 2024 |
Total number of edits | 113 |
Total number of distinct authors | 20 |
Recent number of edits (within past 90 days) | 3 |
Recent number of distinct authors | 1 |
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Facts about "Cascade Lake - Microarchitectures - Intel"
codename | Cascade Lake + |
core count | 2 +, 4 +, 6 +, 8 +, 10 +, 12 +, 16 +, 18 +, 20 +, 22 +, 24 +, 26 +, 28 +, 32 +, 48 + and 56 + |
designer | Intel + |
first launched | 2019 + |
full page name | intel/microarchitectures/cascade lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Cascade Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |