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'''Machine Learning Unit''' ('''MLU''') is a family of [[neural processors]] designed by [[Cambricon]].
 
'''Machine Learning Unit''' ('''MLU''') is a family of [[neural processors]] designed by [[Cambricon]].
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== Overview ==
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Announced in late 2017, the MLU family of [[neural processors]] designed for cloud-based workloads for both inference and training. In contrast to Cambricon's mobile and edge computing [[IP cores]], those processors have a higher power evenlope and are designed for much higher performance.
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== Models ==
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{{empty section}}
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== See also ==
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* Google's {{google|TPU}}

Revision as of 01:03, 27 May 2018

MLU
Developer Cambricon
Manufacturer TSMC
Type Neural Processors
Introduction Nov 7, 2017 (announced)
May 3, 2018 (launch)
ISA MLU
Word size 64 bit
8 octets
16 nibbles
Process 16 nm
0.016 μm
1.6e-5 mm
Technology CMOS
Clock 1,000 MHz-1,300 MHz

Machine Learning Unit (MLU) is a family of neural processors designed by Cambricon.

Overview

Announced in late 2017, the MLU family of neural processors designed for cloud-based workloads for both inference and training. In contrast to Cambricon's mobile and edge computing IP cores, those processors have a higher power evenlope and are designed for much higher performance.

Models

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See also

Retrieved from "https://en.wikichip.org/w/index.php?title=cambricon/mlu&oldid=78813"
Facts about "Machine Learning Unit (MLU) - Cambricon"
RDF feed
designerCambricon +
first announcedNovember 7, 2017 +
first launchedMay 3, 2018 +
full page namecambricon/mlu +
instance ofintegrated circuit family +
instruction set architectureMLU +
main designerCambricon +
manufacturerTSMC +
nameMLU +
process16 nm (0.016 μm, 1.6e-5 mm) +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +