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Difference between revisions of "arm holdings/microarchitectures/cortex-a76"
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#REDIRECT [[arm holdings/microarchitectures/ares]]
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{{armh title|Cortex-A76 (Ares)|arch}}
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{{microarchitecture
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|atype=CPU
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|name=Cortex-A76
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|designer=ARM Holdings
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|manufacturer=TSMC
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|introduction=May 31, 2018
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|process=10 nm
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|process 2=7 nm
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|cores=1
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|cores 2=2
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|cores 3=4
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|oooe=Yes
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|speculative=Yes
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|renaming=Yes
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|stages min=11
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|stages max=13
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|decode=4-way
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|isa=ARMv8.2
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|feature=Hardware virtualization
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|extension=FPU
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|extension 2=NEON
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|l1i=8-64 KiB
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|l1i per=core
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|l1i desc=4-way set associative
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|l1d=8-64 KiB
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|l1d per=core
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|l1d desc=4-way set associative
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|l2=64-256-512 KiB
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|l2 per=core
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|l3=0-4 MiB
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|l3 per=Cluster
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|predecessor=Cortex-A75
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|predecessor link=arm holdings/microarchitectures/prometheus
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|successor=Deimos
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|successor link=arm holdings/microarchitectures/deimos
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}}
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'''Cortex-A76''' is the successor to the {{armh|Cortex-A75|l=arch}}, a low-power high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A76, which implemented the {{arm|ARMv8.2}} ISA, is the a performant core which is often combined with a number of lower power cores (e.g. {{\\|Cortex-A55}}) in a {{armh|DynamIQ big.LITTLE}} configuration to achieve better energy/performance.

Revision as of 17:35, 8 September 2018

Edit Values
Cortex-A76 µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC
IntroductionMay 31, 2018
Process10 nm, 7 nm
Core Configs1, 2, 4
Pipeline
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages11-13
Decode4-way
Instructions
ISAARMv8.2
ExtensionsFPU, NEON
Cache
L1I Cache8-64 KiB/core
4-way set associative
L1D Cache8-64 KiB/core
4-way set associative
L2 Cache64-256-512 KiB/core
L3 Cache0-4 MiB/Cluster
Succession

Cortex-A76 is the successor to the Cortex-A75, a low-power high-performance ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A76, which implemented the ARMv8.2 ISA, is the a performant core which is often combined with a number of lower power cores (e.g. Cortex-A55) in a DynamIQ big.LITTLE configuration to achieve better energy/performance.

Retrieved from "https://en.wikichip.org/w/index.php?title=arm_holdings/microarchitectures/cortex-a76&oldid=82221"
Facts about "Cortex-A76 - Microarchitectures - ARM"
RDF feed
codenameCortex-A76 +
core count1 +, 2 + and 4 +
designerARM Holdings +
first launchedMay 31, 2018 +
full page namearm holdings/microarchitectures/cortex-a76 +
instance ofmicroarchitecture +
instruction set architectureARMv8.2 +
manufacturerTSMC +
microarchitecture typeCPU +
nameCortex-A76 +
pipeline stages (max)13 +
pipeline stages (min)11 +
process10 nm (0.01 μm, 1.0e-5 mm) + and 7 nm (0.007 μm, 7.0e-6 mm) +