Zen 5 - Microarchitectures - AMD

	Edit Values
	Zen 5 µarch
	General Info
Arch Type	CPU
Designer	AMD
Manufacturer	TSMC or Samsung
Process	3 nm
Core Configs	256, 224, 192, 144, 128, 96, 72, 64, 56, 48, 32, 28, "P/12E" can not be assigned to a declared number type with value 24.24P/12E, "P/8E" can not be assigned to a declared number type with value 16.16P/8E, "P/6E" can not be assigned to a declared number type with value 12.12P/6E, "P/4E" can not be assigned to a declared number type with value 8.8P/4E
PE Configs	256, 224, 384, 288, 256, 192, 144, 128, 112, 96, 64, 56, 60, 40, 30, 20
	Pipeline
Type	Superscalar
OoOE	Yes
Speculative	Yes
Reg Renaming	Yes
	Instructions
ISA	x86-64, AVX512, AMX (Advanced Matrix Extensions)
	Cores
Core Names	Turin (EPYC server multiprocessor),; Da Vinci (Threadripper Workstation),; Granite Ridge (Gaming Desktop CPU),; Strix Point (Gaming APU with RDNA3 or RDNA4)
	Succession
	Zen 4

Zen 5 is a planned microarchitecture being developed by AMD as a successor to Zen 4.

History

Zen 5 was first mentioned by lead architect Michael Clark during a discussion on April 9th, 2018^[1].

Zen 5 is speculated to be produced on a 5nm process.

This section is empty; you can help add the missing info by editing this page.

Nothing is currently known about the architectural improvements that are being done to Zen 5.

This section is empty; you can help add the missing info by editing this page.

codename	Zen 5 +
core count	256 +, 224 +, 192 +, 144 +, 128 +, 96 +, 72 +, 64 +, 56 +, 48 +, 32 + and 28 +
designer	AMD +
full page name	amd/microarchitectures/zen 5 +
instance of	microarchitecture +
instruction set architecture	x86-64 + and AVX512, AMX (Advanced Matrix Extensions) +
manufacturer	TSMC or Samsung +
microarchitecture type	CPU +
name	Zen 5 +
process	3 nm (0.003 μm, 3.0e-6 mm) +
processing element count	256 +, 224 +, 384 +, 288 +, 192 +, 144 +, 128 +, 112 +, 96 +, 64 +, 56 +, 60 +, 40 +, 30 + and 20 +