...]s. These architectures typically have a matching [[register file]] with [[registers]] width of 32 bits. === [[x86]] ===

...]s. These architectures typically have a matching [[register file]] with [[registers]] width of 64 bits. === [[x86]] ===

| registers = 7 ...an {{arch|8}} data and address bus. This architecture included seven 8-bit registers, 48 instructions, and interrupt capability.

|isa=x86-64 ...as|Austin]] - [[wikipedia:Mount Bonnell|Mount Bonnell]], was Intel's first x86-compatible [[microarchitecture]] designed to target the ultra-low power mar

|isa=x86-64 ...s and many ALU operations have 3 op/cycle throughput for 16, 32 and 64-bit registers. (8-bit ALU ops throughput is 2, 1.5 or 1 op per cycle).

|isa=x86-64 * New memory model for {{x86|TSX|Transactional Synchronization Extensions}}

|isa=x86-64 ! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AES}} !! [[IGP]] !! {{intel|Turbo Boost|TBT}} !! [[ECC]]

|isa=x86-64 ! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]]

|isa=x86-64 Ice Lake introduced a number of {{x86|extensions|new instructions}}.

{{x86 title|UMIP}}{{x86 isa main}} '''User-Mode Instruction Prevention''' (UMIP) is an x86 security feature introduced in the Intel {{intel|Cannon Lake}}, {{intel|Gol

|isa=x86-32 *** Short decode: Two x86 instructions that generate up to two micro-ops each

|isa=x86-64 ! Cores !! Unlocked !! {{x86|AVX2}} !! [[SMT]] !! {{amd|XFR}} !! [[IGP]] !! [[ECC]] !! [[Multiprocessin

|isa=x86-64 ! Cores !! Unlocked !! {{x86|AVX2}} !! [[SMT]] !! [[IGP]] !! [[ECC]] !! [[Multiprocessing|MP]]

{{x86 isa main}} ...re is widely used in the [[desktop]] and [[server]] markets. Today, custom x86-based implementations are designed by a number of [[semiconductor companies

| isa = x86-64 '''Xeon E5''' is a family of mid-range enterprise-level [[x86]] microprocessors. These server processors offer high performance, multi-so

{{x86 title|Extensions}}{{x86 isa main}} The [[x86]] [[instruction set architecture|ISA]] has gone through numerous iterations

** Early zero bubble predictor using Target Address Registers controlled by the compiler ...d that must determine variable length instruction boundaries and translate x86 instructions into internal micro-ops. In contrast, Merced fetches fixed len

{{x86 title|Advanced Vector Extensions 512 (AVX-512)}}{{x86 isa main}} ...ber of {{arch|512}} [[SIMD]] [[x86]] [[instruction set]] extensions. The {{x86|extensions}} were formally introduced by [[Intel]] in July [[2013]] with fi

=== Registers === * [[x86]]

{{x86 title|Total Memory Encryption (TME)}}{{x86 isa main}} ...emory Encryption''' ('''TME''') is a planned [[x86]] [[instruction set]] {{x86|extension}} proposed by [[Intel]] for a full physical memory encryption for

...hitect of [[AMD]]'s {{amd|Bobcat|l=arch}} microarchitecture, a low-power [[x86]] design. ...or some special cases such as in {{arm|ARMv7}} where four single-precision registers can alias into a single quad register or a pair of doubles, M1 has special

SB-TSI was first implemented on processors of the {{amd|CPUID|x86 CPU Family}} 10h, augmenting and later replacing pins which provide direct ...e analog signal from a thermal diode and has various control registers and registers to read out the current temperature and alert status. The temperature is pr

...oarchitecture with advanced dynamic branch prediction, 4-way decoding of [[x86]] instructions with a stack optimizer, multiple caches including an Op cach * {{x86|AVX-512}} instructions support, 256-bit data path<ref name="ryzen-7000-prev

|isa=x86-64 |isa family=x86

...ta center]] markets. The CSA is designed to work alongside a traditional [[x86]] core and serve as an [[acceleration engine]]. The configurable spatial accelerators are designed alongside a traditional [[x86]] core. This allows the cores maintain legacy support and handle additional

** Relies on an [[x86]] host ...tural registers|architectural vector registers]] (VRs) onto 256 [[physical registers]]. There is support for enhanced preloading and avoids [[WAR]]/[[WAW]] depe

|isa=x86-64 ...'''), the successor to {{\\|Palm Cove}}, is a high-performance [[10 nm]] [[x86]]-64 core microarchitecture designed by [[Intel]] for an array of server an

|isa=x86-64 '''CHA''' is a [[16-nanometer]] [[x86]] SoC microarchitecture designed by [[Centaur Technology]] for the server m

{{x86 title|AVX-512 BFloat16 Instructions (BF16)}}{{x86 isa main}} ...t16 Instructions''' ('''AVX512_BF16''') is an [[x86]] extension, part of {{x86|AVX-512}}, designed to accelerate neural network-based [[algorithms]] by pe

{{x86 title|Advanced Matrix Extension (AMX)}}{{x86 isa main}} '''Advanced Matrix Extension''' ('''AMX''') is an [[x86]] {{x86|extension}} that introduces a matrix register file and new instructions for

...512 Vector Neural Network Instructions Word Variable Precision (4VNNIW)}}{{x86 isa main}} ...ecision''' ('''AVX512_4VNNIW''') is an [[x86]] extension and part of the {{x86|AVX-512}} [[SIMD]] instruction set.

...itle|AVX-512 Fused Multiply-Accumulate Packed Single Precision (4FMAPS)}}{{x86 isa main}} ...ecision''' ('''AVX512_4FMAPS''') is an [[x86]] extension and part of the {{x86|AVX-512}} [[SIMD]] instruction set.