{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}} |l1i extra=(per core, write-back)

| microarch 2 = Skylake (server) [[File:broadwell de (back).png|225px|right]]

|extension 20=VT-x |successor=Skylake (client)

|extension 20=VT-x [[File:haswell buff window.png|right|350px]]

{{intel title|Skylake (client)|arch}} |name=Skylake (client)

|extension 20=VT-x |core name 8=Kaby Lake X

|extension 20=VT-x === Key changes from {{\\|Cannon Lake}}/{{\\|Skylake}}===

| [[ICC]] || <code>-march=skylake</code> || <code>-mtune=skylake</code> | [[GCC]] || <code>-march=skylake</code> || <code>-mtune=skylake</code>

[[File:amd-zen-black-logo.png|right|Zen Logo]] [[File:amd ryzen black bg logo.png|thumb|right|Ryzen brand logo]]

{{intel title|Kaby Lake X|core}} |name=Kaby Lake X

|image 2=kaby lake dt (back).png |predecessor=Skylake DT

{{intel title|Skylake X|core}} |name=Skylake X

|image=skylake x (front).png |microarch=Skylake (server)

|image=skylake x (front).png |microarch=Skylake (server)

|image=skylake x (front).png |microarch=Skylake (server)

|image=skylake x (front).png |microarch=Skylake (server)

|image=skylake x (front).png |microarch=Skylake (server)

|image=skylake x (front).png |microarch=Skylake (server)

{{intel title|Skylake DT|core}} |name=Skylake DT

{{intel title|Skylake (server)|arch}} |name=Skylake (server)

|image 2=broadwell e (back).png |caption 2=Package back

|image 2=kaby lake r (back).png |caption 2=Package back side

|extension 20=VT-x |core name=Cascade Lake X

...ata[array[input]];</code> until the value of <code>array_size</code> comes back to indicate that the processor speculated incorrectly. When this happens, t ...tantial delay until the value as a result of the [[cache miss]] is brought back from [[DRAM]]. During this time, the processor will [[speculative execution

...architecture. In mid-[[2017]] Intel launched the {{intel|Skylake (server)|Skylake server microarchitecture|l=arch}} which featured also featured the mesh int Tiles are replicated in the X and Y axis as many times as desired. The type of tile depends on the design

|extension 20=VT-x | [[ICC]] || <code>-march=skylake</code> || <code>-mtune=skylake</code>

[[File:next-horizon-zen3-4-roadmap.png|right|thumb|400px|Zen 4 on the roadmap.]] ...F}} - Foundation (first introduced with [[Intel]] {{intel|skylake (server)|Skylake|l=arch}})

{{intel title|Skylake X Refresh|core}} |name=Skylake X Refresh

|image=skylake x (front).png |microarch=Skylake (server)

|image=skylake x (front).png |microarch=Skylake (server)

|image=skylake x (front).png |microarch=Skylake (server)

|image=skylake x (front).png |microarch=Skylake (server)

|image=skylake x (front).png |microarch=Skylake (server)

|image=skylake x (front).png |microarch=Skylake (server)

|image=skylake x (front).png |microarch=Skylake (server)

|extension 20=VT-x [[File:sunny cove roadmap.png|thumb|right|200px|Intel Core roadmap]]

|extension 20=VT-x |predecessor=Skylake

|image=skylake x (front).png |microarch=Skylake (server)

***** 256 x 128-bit instructions ***** 2 banks x 256 x 128-bit instructions