! Language !! Compiler !! Function | [[ARM]] || [[NEON]] || VCNT ||

== Compiler support == ! Compiler !! Arch-Specific || Arch-Favorable

...|| Trailing Bit Manipulation; bit manipulation instructions designed to be compiler intrinsics * {{arm|Versions|ARM's Versions}}

|designer=ARM Holdings ...to the {{armh|Cortex-A7|l=arch}}. The Cortex-A53, which implemented the {{arm|ARMv8}} ISA, is typically found in entry-level smartphone and other embedde

'''Falkor''' is an [[ARM]] microarchitecture designed by [[Qualcomm]] for the server market. Falkor- == Compiler Support ==

|designer=ARM Holdings ...be implemented in their own chips. The Cortex-A75, which implemented the {{arm|ARMv8.2}} ISA, is the a performant core which is often combined with a numb

...ructed piece of [[JavaScript]] can running on a browser that has a [[JIT]] compiler can be used to leak the entire memory of its parent process (i.e. the brows ...gs|ARM]] || {{armh|Cortex-R7|l=arch}} || rowspan="10" | [https://developer.arm.com/support/security-update Post]

.... This was Samsung's first in-house developed high-performance low-power [[ARM]] microarchitecture. == Compiler support ==

...e 2''' ('''M2''') is the successor to the {{\\|Mongoose 1}}, a [[10 nm]] [[ARM]] microarchitecture designed by [[Samsung]] for their consumer electronics. == Compiler support ==

...' ('''Meerkat''') is the successor to the {{\\|Mongoose 2}}, a [[10 nm]] [[ARM]] microarchitecture designed by [[Samsung]] for their consumer electronics. == Compiler support ==

'''Vulcan''' is a [[16 nm]] high-performance {{arch|64}} [[ARM]] microarchitecture designed by [[Broadcom]] and later introduced by [[Cavi ...outcome of this effort which involved adapting the existing core to the [[ARM]] ISA instead of [[MIPS]] and enhancing the cores in various ways. Vulcan d

...nos M4''' ('''Cheetah''') is the successor to the {{\\|M3}}, an [[8 nm]] [[ARM]] microarchitecture designed by [[Samsung]] for their consumer electronics. == Compiler support ==

|designer=ARM Holdings ...Ares''') is a high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the server market. This microarchitecture is designed as a s

|designer=ARM Holdings |predecessor link=arm holdings/microarchitectures/cortex-a75

|designer=ARM Holdings |predecessor link=arm holdings/microarchitectures/cortex-a76

|designer=ARM Holdings |predecessor link=arm holdings/microarchitectures/cortex-a77

'''eMAG''' is a family of {{arch|64}} high-performance [[ARM]] server microprocessors designed by [[Ampere Computing]] for the data cent eMAG is a family of high-performance [[ARM]] server processors designed by [[Ampere Computing]] and introduced in [[20

'''ThunderX''' is a family of {{arch|64}} [[multi-core]] [[ARM]] server microprocessors introduced by [[Cavium]]. == Compiler Support ==

|designer=ARM Holdings ...be implemented in their own chips. The Cortex-A73, which implemented the {{arm|ARMv8}} ISA, is the performance core which is often combined with a number

|designer=ARM Holdings ...be implemented in their own chips. The Cortex-A72, which implemented the {{arm|ARMv8}} ISA, is a performant core which is often combined with a number of

|designer=ARM Holdings ...be implemented in their own chips. The Cortex-A57, which implemented the {{arm|ARMv8}} ISA, is the a performant core which is often combined with a number

|designer=ARM Holdings ..., a low-power high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a s

|designer=ARM Holdings ...rch}}, a low-power performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a s

|designer=ARM Holdings ...es to be implemented in their own chips. The Cortex-A8 was designed by the Arm Austin design center.

...M5''' ('''Lion''') is the successor to the {{\\|Mongoose 4}}, a [[7 nm]] [[ARM]] microarchitecture designed by [[Samsung]] for their consumer electronics. == Compiler support ==

|isa family=ARM ...ode]] boiled down to cost and IP readiness. There are twelve {{arch|64}} [[ARM]] cores organized as three clusters of quad-core {{armh|Cortex-A72|l=arch}}

|designer=Arm Holdings ...is a first-generation [[neural processor]] microarchitecture designed by [[Arm]] for embedded and mobile SoCs as part of {{armh|Project Trillium}}. This m

|32035||3.22||[https://www.amd.com/system/files/TechDocs/32035.pdf Compiler Usage Guidelines for AMD64 Platforms Application Note]||2007-11-01|| === ARM based ===

|designer=ARM Holdings ...be implemented in their own chips. The Cortex-M55, which implements the {{arm|ARMv8.1-M}} ISA, is an ultra-low-power core which is often found in microco

|designer=ARM Holdings |successor link=arm holdings/microarchitectures/cortex-x2