• samsung/microarchitectures/m1
  ** 4-way instruction decode * Cache
  13 KB (1,962 words) - 14:48, 21 February 2019
• samsung/microarchitectures/m3
  *** Larger [[instruction queue]] (40 entries, up from 24) *** Larger [[instruction fetch]] (48B/cycle, up from 24B/cycle)
  20 KB (3,149 words) - 10:44, 15 February 2020
• greenwaves/gap8
  ...ssary. This core has its own 16 KiB of data cache and 4 KiB of instruction cache. ...programmed using the familiar standard GCC/GDB toolchain derived from the one developed by the RISC-V foundation. Currently two real-time operating syste
  6 KB (981 words) - 14:11, 28 February 2018
• intel/microarchitectures/polaris
  ...words can be transferred each cycle between the register file and the data cache. Additionally, up to four 32-bit data words can be issued to the two FMA un ...54]] [[single-precision]] operands and is designed to sustain a single FMA instruction every 250ps (4 GHz). The multiplier itself is a [[Wallace tree]] of 4-2 car
  16 KB (2,552 words) - 23:22, 17 May 2019
• cavium/microarchitectures/vulcan
  *** Half L2 Cache Size (256 KiB, down form 512 KiB) * Cache
  17 KB (2,449 words) - 22:11, 4 October 2019
• samsung/microarchitectures/m4
  ** Larger [[instruction queue]] (48 entries, up from 40) * Cache
  5 KB (680 words) - 14:43, 16 March 2023
• intel/microarchitectures/comet lake
  ** 25% more [[last level cache]] (up to 20 MiB, up from 16 MiB) * Cache
  10 KB (1,357 words) - 18:48, 13 September 2022
• amd/microarchitectures/zen 4
  Zen 4 was first mentioned by Forrest Norrod during AMD's EPYC One Year Anniversary webinar. During the next horizon event which was held on N ...4c [referred to as “Zen 4D” in leaks] core sacrificing half of the L3 cache.)
  13 KB (1,821 words) - 19:28, 13 November 2023
• arm holdings/microarchitectures/neoverse n1
  The Neoverse N1 has a private L1I, L1D, and L2 cache. * Cache
  7 KB (980 words) - 13:46, 18 February 2023
• arm holdings/microarchitectures/cortex-a76
  *** Decoupled from the instruction fetch The Cortex-A76 has a private L1I, L1D, and L2 cache.
  14 KB (2,183 words) - 17:15, 17 October 2020
• arm holdings/microarchitectures/cortex-a77
  ** New [[L0]] MOP cache ** 1.5x wider instruction fetch (6 instrs/cycle, up from 4)
  17 KB (2,555 words) - 06:08, 16 June 2023
• arm holdings/microarchitectures/cortex-a78
  ** Additional instruction fusion cases **** New packaging scheme (improve instruction density)
  21 KB (3,067 words) - 09:25, 31 March 2022
• arm/armv8
  ...ced in [[2011]] which brought a large number of fundamental changes to the instruction set, including the introduction of 64-bit operating capabilities. ...what was previously {{\\|ARMv7}}. It covers the {{\\|A32}} and {{\\|T32}} instruction sets along with a number of new instructions. AArch32 keeps the classical A
  6 KB (817 words) - 06:37, 24 April 2020
• intel/configurable spatial accelerator
  ...s full languages such as C++ and executes full programs. There is a one-to-one correspondence between the nodes in the compiler-generated graph and the CS ...are configured. The CSA can be partitioned into [[privileged]] and [[user-level]] state. This can allow a primary configuration of the fabric to run withou
  14 KB (2,130 words) - 20:19, 2 October 2018
• nec/microarchitectures/sx-aurora
  ...er 26 2017 with a complete lineup that ranges from a workstation featuring one vector engine (VE) card to a full supercomputer with 64 VEs. NEC disclosed *** L1I Cache:
  16 KB (2,497 words) - 13:30, 15 May 2020
• intel/microarchitectures/sunny cove
  ** 1.5x larger µOP cache (2.3K entries, up from 1536) ** Data Cache
  34 KB (5,187 words) - 06:27, 17 February 2023
• arm holdings/microarchitectures/cortex-a15
  One can specify {{arm|NEON}} support using the <code>-mfpu=neon</code> option. ** Level 1 instruction cache switched to [[PIPT]] (from [[VIPT]])
  3 KB (347 words) - 14:40, 31 December 2018
• arm holdings/microarchitectures/arm9/pr1
  "As one of the leading vendors of embedded ARM7TDMI applications, with extensive ex ...ction regions. These can be specified as to base address, region size, and cache/buffer properties. During debug, the ARM940T provides full debug access to
  8 KB (1,261 words) - 22:05, 29 December 2018
• samsung/microarchitectures/m5
  ** Larger [[instruction queue]] (60 entries, up from 48) * Cache
  3 KB (333 words) - 22:10, 27 July 2021
• hisilicon/microarchitectures/taishan v110
  * Cache ** L1I Cache
  7 KB (947 words) - 10:20, 9 September 2022

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