• intel/cores/cascade lake sp
  ...for neural network / deep learning workloads, and introduces [[persistent memory]] support. Cascade Lake SP-based chips are manufactured on an enhanced [[14 ...extended memory models. Cascade Lake also brings support for [[persistent memory]].
  9 KB (1,291 words) - 13:48, 27 February 2020
• amd/packages/socket tr4
  ...r RDIMMs, while TR4 and sTRX4 processors support only UDIMMs on up to four memory channels. TR4 and sTRX4 omit four of eight PCIe interfaces present on Socke It supports four channels of 72-bit [[DDR4]] memory with up to two DIMMs per channel, four 16-lane PCIe Gen 3 I/O interfaces, e
  86 KB (17,313 words) - 02:48, 13 March 2023
• intel/cores/skylake x refresh
  ...} and use the {{intel|Lewisburg}} chipset ({{intel|Platform Controller Hub|HUB}}). * Quad-channel Memory
  3 KB (391 words) - 10:17, 24 October 2018
• amd/cores/genoa
  === Memory Interface === ...(32 data, 8 ECC) DDR5 subchannels. The memory controllers support {{wp|ECC memory}} (80b x4, 80b x8, and 72b x4 ECC, i.e. EC4 and EC8 DIMMs) and DDR5 DRAMs w
  14 KB (1,983 words) - 01:41, 2 April 2023
• intel/cores/coffee lake hr
  ...440|BGA-1440}} and use 300-series chipset ({{intel|Platform Controller Hub|HUB}}). The microprocessor is connected to the chipset via 4 of the chip's 20 P * Dual-channel Memory
  4 KB (507 words) - 07:45, 5 May 2019
• amd/List of AMD publications
  |16294||A||White Paper: The Effect of Local Buffer Memory Size on FDDI Throughput||1992-01|| |17692||A||ISA-HUB-KT||1993-01-31||
  181 KB (24,861 words) - 16:02, 17 April 2022
• intel/cores/cascade lake r
  ...for neural network / deep learning workloads, and introduces [[persistent memory]] support. Cascade Lake R-based chips are manufactured on an enhanced [[14 ...Those use the {{intel|Lewisburg}} chipset ({{intel|Platform Controller Hub|HUB}}) via 4 PCIe3 lanes using Intel's proprietary {{intel|Direct Media Interfa
  8 KB (1,098 words) - 11:25, 28 February 2020
• amd/packages/ft3
  ...essors with an integrated north bridge, graphics processor, and controller hub. Its counterpart for desktop processors is the PGA-721 package for {{\\|Soc ** AMD Memory Controller PowerCap
  5 KB (645 words) - 16:31, 16 March 2023
• amd/packages/ft3b
  ...essors with an integrated north bridge, graphics processor, and controller hub targeting the notebook, tablet, all-in-one desktop, and embedded segment. F ** AMD Memory Controller PowerCap
  4 KB (610 words) - 16:33, 16 March 2023
• amd/packages/socket am1
  ...essors with an integrated north bridge, graphics processor, and controller hub targeting the value segment. Its counterpart for mobile and embedded proces ** AMD Memory Controller PowerCap
  5 KB (642 words) - 14:08, 7 September 2020
• amd/List of AMD CPU sockets
  ! MC<ref>If processors for this socket integrate a Memory Controller, the number of independent channels times the maximum channel width in bits ! I/O lanes<ref>FSB = Front Side Bus (memory and I/O interfaces provided by the chipset), HTx = HyperTransport generatio
  17 KB (2,543 words) - 03:01, 17 May 2023
• amd/packages/fp6
  .../72-bit channels of [[DDR4]] memory or four 32-bit channels of [[LPDDR4x]] memory, two PCIe Gen 3 I/O interfaces with 20 lanes total, four digital display in ...CPU cores, two memory controllers, a graphics processor, and a controller hub. "Renoir" and "Cezanne" processors are also available in a desktop processo
  20 KB (3,273 words) - 17:47, 10 May 2023
• amd/packages/socket swrx8
  ...memory channel. TR4 and sTRX4 processors support only UDIMMs on up to four memory channels, but up to two DIMMs per channel like Socket SP3, and omit four of ...ocessors are compatible with sWRX8 platforms or vice versa, given suitable memory and firmware, is unclear.
  11 KB (1,577 words) - 02:53, 13 March 2023
• amd/packages/socket strx4
  ...r RDIMMs, while TR4 and sTRX4 processors support only UDIMMs on up to four memory channels. TR4 and sTRX4 omit four of eight PCIe interfaces present on Socke ...gle socket client infrastructure supports four channels of 72-bit [[DDR4]] memory with up to two {{abbr|UDIMM}}s per channel, four 16-lane PCIe Gen 4 I/O lin
  14 KB (2,188 words) - 11:45, 6 April 2024
• amd/packages/socket am5
  Socket AM5 supports two channels of [[DDR5]] memory with two 36-bit subchannels (32 bit data + 4 bit ECC) and up to 2 DIMMs per ...e generally used to access firmware ({{abbr|PSP}} ROM and BIOS) i.e. flash memory, and a {{abbr|TPM}}. It is worth noting that the PSP can also provide TPM s
  19 KB (3,162 words) - 17:35, 11 May 2023

View (previous 20 | next 20) (20 | 50 | 100 | 250 | 500)