• arm holdings/microarchitectures/cortex-a73
  ...the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in th === Block Diagram ===
  2 KB (205 words) - 23:49, 4 April 2021
• arm holdings/microarchitectures/cortex-a72
  ...the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in th === Block Diagram ===
  2 KB (291 words) - 15:57, 4 July 2022
• arm holdings/microarchitectures/cortex-a57
  ...the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in th === Block Diagram ===
  4 KB (474 words) - 21:13, 25 April 2021
• arm holdings/microarchitectures/cortex-a15
  ...the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in th === Block Diagram ===
  3 KB (347 words) - 14:40, 31 December 2018
• arm holdings/microarchitectures/cortex-a8
  ...ldings]] for the mobile market. This microarchitecture is designed as an [[IP core]] and is sold to other semiconductor companies to be implemented in th === Block Diagram ===
  3 KB (428 words) - 14:30, 31 December 2018
• arm holdings/microarchitectures/cortex-a7
  ...the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in th === Block Diagram ===
  2 KB (275 words) - 14:24, 31 December 2018
• arm holdings/microarchitectures/cortex-a12
  ...the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in th === Block Diagram ===
  1 KB (167 words) - 14:25, 31 December 2018
• arm holdings/microarchitectures/cortex-a17
  ...the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in th === Block Diagram ===
  2 KB (184 words) - 14:25, 31 December 2018
• arm holdings/microarchitectures/cortex-a5
  ...the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in th === Block Diagram ===
  1 KB (159 words) - 14:25, 31 December 2018
• arm holdings/microarchitectures/arm11
  ...ldings]] for the mobile market. This microarchitecture is designed as an [[IP core]] and is sold to other semiconductor companies to be implemented in th === Block Diagram ===
  2 KB (202 words) - 05:05, 31 December 2018
• arm holdings/microarchitectures/arm9
  ...ldings]] for the mobile market. This microarchitecture is designed as an [[IP core]] and is sold to other semiconductor companies to be implemented in th === Block Diagram ===
  4 KB (391 words) - 03:45, 9 October 2020
• tesla (car company)/fsd chip
  [[File:tesla fsd block diagram.svg|left|300px|thumb|Block Diagram]] ...ad of a more [[technology node|leading-edge node]] boiled down to cost and IP readiness. There are twelve {{arch|64}} [[ARM]] cores organized as three cl
  13 KB (1,952 words) - 20:34, 16 September 2023
• intel/microarchitectures/spring hill
  ...ce Lake (Client)|Ice Lake|l=arch}} SoC design and makes extensive reuse of IP throughput the chip. === Block Diagram ===
  9 KB (1,292 words) - 08:41, 26 March 2020
• arm holdings/microarchitectures/mlp
  ...ject Trillium}}. This microarchitecture is designed as a synthesizable NPU IP and is sold to other semiconductor companies to be implemented in their own Although the MLP is designed as a synthesizable IP, it has been specifically tuned for the [[16 nanometer]] and [[7 nanometer]
  9 KB (1,379 words) - 22:35, 6 February 2020
• arm holdings/microarchitectures/cortex-m55
  ...bedded subsystems. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in th === Block Diagram ===
  12 KB (1,806 words) - 10:51, 12 January 2021
• arm holdings/microarchitectures/neoverse v1
  ...omputing]] market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in th === Block Diagram ===
  5 KB (748 words) - 16:20, 4 July 2022
• arm holdings/microarchitectures/cortex-a510
  Note that this microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in th === Block Diagram ===
  15 KB (2,282 words) - 11:20, 10 January 2023
• alchemy/alchemy
  The Security Engine accelerates IP packet encryption/decryption in hardware. * AES-128 encryption/decryption in hardware with ECB, CBC, CFB, and OFB block cipher modes (Au1200 and Au1250 only)
  31 KB (4,972 words) - 03:09, 20 March 2022

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