• samsung/microarchitectures/m3
  *** New mid-level DTLB ...icated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally, there is a unified L2 TLB (STLB).
  20 KB (3,149 words) - 10:44, 15 February 2020
• cavium/microarchitectures/vulcan
  *** DTLB
  17 KB (2,449 words) - 22:11, 4 October 2019
• samsung/microarchitectures/m4
  ...icated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally, there is a unified L2 TLB (STLB). ** DTLB
  5 KB (680 words) - 14:43, 16 March 2023
• intel/microarchitectures/comet lake
  ...icated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB). ** DTLB
  10 KB (1,357 words) - 18:48, 13 September 2022
• amd/microarchitectures/zen 4
  * L1 and L2 DTLB size increased from 64 to 72 and 2,048 to 3,072 entries * DTLB
  13 KB (1,821 words) - 19:28, 13 November 2023
• arm holdings/microarchitectures/neoverse n1
  ...icated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally, there is a unified L2 TLB (STLB). ** DTLB
  7 KB (980 words) - 13:46, 18 February 2023
• arm holdings/microarchitectures/cortex-a76
  ...icated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally, there is a unified L2 TLB (STLB). ** DTLB
  14 KB (2,183 words) - 17:15, 17 October 2020
• arm holdings/microarchitectures/cortex-a77
  ...icated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally, there is a unified L2 TLB (STLB). ** DTLB
  17 KB (2,555 words) - 06:08, 16 June 2023
• arm holdings/microarchitectures/cortex-a78
  ...icated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally, there is a unified L2 TLB (STLB). ** DTLB
  21 KB (3,067 words) - 09:25, 31 March 2022
• intel/microarchitectures/sunny cove
  *** DTLB now split for load and stores **** DTLB 4 KiB TLB competitively shared (from fixed partitioning)
  34 KB (5,187 words) - 06:27, 17 February 2023
• arm holdings/microarchitectures/cortex-a8
  ** DTLB
  3 KB (428 words) - 14:30, 31 December 2018
• samsung/microarchitectures/m5
  ...icated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally, there is a unified L2 TLB (STLB). ** DTLB
  3 KB (333 words) - 22:10, 27 July 2021
• intel/microarchitectures/palm cove
  ...icated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB). ** DTLB
  5 KB (718 words) - 13:56, 9 May 2019
• ibm/microarchitectures/z15
  ** DTLB
  7 KB (912 words) - 16:31, 7 May 2020
• arm holdings/microarchitectures/neoverse v1
  ...icated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally, there is a unified L2 TLB (STLB). ** DTLB
  5 KB (748 words) - 16:20, 4 July 2022
• arm holdings/microarchitectures/cortex-a510
  The Cortex-A510 features an instruction TLB (ITLB) and data TLB (DTLB) which are private to each core and an L2 TLB that is private to the core c ** DTLB
  15 KB (2,282 words) - 11:20, 10 January 2023

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