* Platform Controller Hub (PCH) * New memory model for {{x86|TSX|Transactional Synchronization Extensions}}

** Memory Subsystem ** Dropped {{intel|QPI}} controller which linked the two dies

** Intel Sensor Solution Hub integration ** Memory Subsystem

* Memory ** Faster memory for mainstream desktops (i.e., {{intel|Kaby Lake S|l=core}}) DDR4-2400 (fro

Core M dies are packaged with the {{intel|Platform Controller Hub}} (PCH) die in the same packaging which is only about 1 mm thick and requir |?max memory#GB

=== Memory Hierarchy === ...n all four areas of the core (the front end, the execution engine, and the memory subsystem) as well as Zen's new [[SoC]] CCX (CPU Complex) modular design. T

...1}} and use {{intel|Union Point}} chipset ({{intel|Platform Controller Hub|HUB}}) but they may also use previous generation ({{intel|Skylake S|l=core}}) { * Dual-channel Memory

...0}} and use {{intel|Union Point}} chipset ({{intel|Platform Controller Hub|HUB}}) but they may also use previous generation ({{intel|Skylake H|l=core}}) { * Dual-channel Memory

...} and use the {{intel|Lewisburg}} chipset ({{intel|Platform Controller Hub|HUB}}). * Dual-channel Memory

...1}} and use {{intel|Union Point}} chipset ({{intel|Platform Controller Hub|HUB}}) but they may also use previous generation ({{intel|Skylake DT|l=core}}) * Dual-channel Memory

...s supporting hex-chanel 768 GiB of DDR4 ECC memory or 1.5 TiB for extended memory models. ...Those use the {{intel|Lewisburg}} chipset ({{intel|Platform Controller Hub|HUB}}) via 4 PCIe3 lanes using Intel's proprietary {{intel|Direct Media Interfa

...} and use {{intel|Sunrise Point}} chipset ({{intel|Platform Controller Hub|HUB}}). The microprocessor is connected to the chipset via 4 of the chip's 20 P * Dual-channel Memory

...} and use the {{intel|Lewisburg}} chipset ({{intel|Platform Controller Hub|HUB}}). * Quad-channel Memory

...} and use {{intel|Sunrise Point}} chipset ({{intel|Platform Controller Hub|HUB}}). The microprocessor is connected to the chipset via 4 of the chip's 20 P * Dual-channel Memory

...} and use {{intel|Sunrise Point}} chipset ({{intel|Platform Controller Hub|HUB}}). The microprocessor is connected to the chipset via 4 of the chip's 20 P * Dual-channel Memory

...hooking together things such as [[PCIe]] PHYs, [[memory controller]]s, USB hub, and the various computing and execution units. The SDF is a [[superset]] o ...to the cores and to the other peripherals (e.g. memory controller and I/O hub) are routed through the SDF. A key feature of the coherent data fabric is t

...51}} and use {{intel|300-series}} chipset ({{intel|Platform Controller Hub|HUB}}). Despite using the same socket, those chips are not backwards-compatible * Dual-channel Memory

...440|BGA-1440}} and use 300-series chipset ({{intel|Platform Controller Hub|HUB}}). The microprocessor is connected to the chipset via 4 of the chip's 20 P * Dual-channel Memory

|max memory=16 GiB The chip consists of five subsystems: [[NPU]], [[MCU]], Chip Link, Memory, and Peripherals.

...51}} and use {{intel|300-series}} chipset ({{intel|Platform Controller Hub|HUB}}). Despite using the same socket, those chips are not backwards-compatible * Dual-channel Memory

...for neural network / deep learning workloads, and introduces [[persistent memory]] support. Cascade Lake SP-based chips are manufactured on an enhanced [[14 ...extended memory models. Cascade Lake also brings support for [[persistent memory]].

...r RDIMMs, while TR4 and sTRX4 processors support only UDIMMs on up to four memory channels. TR4 and sTRX4 omit four of eight PCIe interfaces present on Socke It supports four channels of 72-bit [[DDR4]] memory with up to two DIMMs per channel, four 16-lane PCIe Gen 3 I/O interfaces, e

...} and use the {{intel|Lewisburg}} chipset ({{intel|Platform Controller Hub|HUB}}). * Quad-channel Memory

=== Memory Interface === ...(32 data, 8 ECC) DDR5 subchannels. The memory controllers support {{wp|ECC memory}} (80b x4, 80b x8, and 72b x4 ECC, i.e. EC4 and EC8 DIMMs) and DDR5 DRAMs w

...440|BGA-1440}} and use 300-series chipset ({{intel|Platform Controller Hub|HUB}}). The microprocessor is connected to the chipset via 4 of the chip's 20 P * Dual-channel Memory

|16294||A||White Paper: The Effect of Local Buffer Memory Size on FDDI Throughput||1992-01|| |17692||A||ISA-HUB-KT||1993-01-31||

...for neural network / deep learning workloads, and introduces [[persistent memory]] support. Cascade Lake R-based chips are manufactured on an enhanced [[14 ...Those use the {{intel|Lewisburg}} chipset ({{intel|Platform Controller Hub|HUB}}) via 4 PCIe3 lanes using Intel's proprietary {{intel|Direct Media Interfa

...essors with an integrated north bridge, graphics processor, and controller hub. Its counterpart for desktop processors is the PGA-721 package for {{\\|Soc ** AMD Memory Controller PowerCap

...essors with an integrated north bridge, graphics processor, and controller hub targeting the notebook, tablet, all-in-one desktop, and embedded segment. F ** AMD Memory Controller PowerCap

...essors with an integrated north bridge, graphics processor, and controller hub targeting the value segment. Its counterpart for mobile and embedded proces ** AMD Memory Controller PowerCap

! MC<ref>If processors for this socket integrate a Memory Controller, the number of independent channels times the maximum channel width in bits ! I/O lanes<ref>FSB = Front Side Bus (memory and I/O interfaces provided by the chipset), HTx = HyperTransport generatio

.../72-bit channels of [[DDR4]] memory or four 32-bit channels of [[LPDDR4x]] memory, two PCIe Gen 3 I/O interfaces with 20 lanes total, four digital display in ...CPU cores, two memory controllers, a graphics processor, and a controller hub. "Renoir" and "Cezanne" processors are also available in a desktop processo

...memory channel. TR4 and sTRX4 processors support only UDIMMs on up to four memory channels, but up to two DIMMs per channel like Socket SP3, and omit four of ...ocessors are compatible with sWRX8 platforms or vice versa, given suitable memory and firmware, is unclear.

...r RDIMMs, while TR4 and sTRX4 processors support only UDIMMs on up to four memory channels. TR4 and sTRX4 omit four of eight PCIe interfaces present on Socke ...gle socket client infrastructure supports four channels of 72-bit [[DDR4]] memory with up to two {{abbr|UDIMM}}s per channel, four 16-lane PCIe Gen 4 I/O lin

Socket AM5 supports two channels of [[DDR5]] memory with two 36-bit subchannels (32 bit data + 4 bit ECC) and up to 2 DIMMs per ...e generally used to access firmware ({{abbr|PSP}} ROM and BIOS) i.e. flash memory, and a {{abbr|TPM}}. It is worth noting that the PSP can also provide TPM s