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Exynos 5433
General Info
Designer	Samsung, ARM Holdings
Manufacturer	Samsung
Model Number	5433
Market	Mobile
Introduction	September 7, 2014 (announced) September 7, 2014 (launched)
General Specs
Family	Exynos
Series	Exynos 7
Frequency	1,900 MHz, 1,300 MHz, 2,340 MHz, 1,101 MHz
Microarchitecture
ISA	ARMv8 (ARM)
Microarchitecture	Cortex-A57, Cortex-A53
Core Name	Cortex-A57, Cortex-A53
Process	20 nm
Technology	CMOS
Die	113 mm²
Word Size	64 bit
Cores	8
Threads	8
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
Vcore	1.00 V-
cTDP down	12 W
cTDP down frequency	1,900 MHz
cTDP up	18 W
cTDP up frequency	2,340 MHz
Tjunction	100°C –

Exynos 5433 is a 64-bit octa-core ARM high performance mobile system on a chip designed by Samsung and introduced in early 2014. The processor is fabricated on Samsung's 20 nm process and features 8 cores in a big.LITTLE configuration consisting of 4 Cortex-A57 big cores and 4 Cortex-A53 little cores. This chip supports up to 3 GiB of dual-channel LPDDR3-1866 memory and incorporates a Mali-T760 MP6 GPU.

Cache

Main articles: Cortex-A57 § Cache and Cortex-A53 § Cache

Cortex-A57 Cluster:

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 320 KiB 327,680 B 0.313 MiB L1I$ 192 KiB 196,608 B 0.188 MiB 4x48 KiB     L1D$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB     L2$ 2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB     1x2 MiB

Cortex-A53 Cluster:

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 256 KiB 262,144 B 0.25 MiB L1I$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB     L1D$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB     L2$ 256 KiB 0.25 MiB 262,144 B 2.441406e-4 GiB     1x1 256 KiB

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type LPDDR3-1866 Supports ECC No Max Mem 3 GiB Controllers 1 Channels 2 Width 32 bit Max Bandwidth 13.91 GiB/s 14,243.84 MiB/s 14.936 GB/s 14,935.749 MB/s 0.0136 TiB/s 0.0149 TB/s Bandwidth Single 6.95 GiB/s Double 13.91 GiB/s

Graphics

[Edit/Modify IGP Info]

	Integrated Graphics Information
	GPU Mali-T760 Designer ARM Holdings Execution Units 6 Max Displays 2 Frequency 700 MHz 0.7 GHz 700,000 KHz Max Resolution   2560x1600 Standards DirectX 11 OpenCL 1.2 OpenGL ES 3.2 OpenVG 1.1 Vulkan 1.0

• Full HD 120fps encoding and decoding
• HEVC decoding, VP8 Codec

Camera

• Front 3.7 MP
• Rear 16 MP

Die

• Samsung 20 nm process
• 113 mm² die size
• Mali-T760 (6 EU)
• Quad-core Cortex-A53 (small cores)
  • 32 KiB L1I$ and 32 KiB L1D$ per core, and a shared 256 KiB L2
  • 4.4 mm² per cluster
    • ~1 mm² per core
    • ~0.55 mm² for 256 KiB L2 cache
• Quad-core Cortex-A57 (big cores)
  • 48KB L1I$ and 32KB L1D$ per core, and a shared 2 MiB L2
  • 15.85 mm² per cluster
    • ~3 mm² per core
    • ~3.87 mm² for 2 MiB L2 cache

Utilizing devices

• Samsung Galaxy Note 4
• Samsung Galaxy Note Edge
• Samsung Galaxy Tab S2

This list is incomplete; you can help by expanding it.

Bibliography

• Pyo, Jungyul, et al. "23.1 20nm high-K metal-gate heterogeneous 64b quad-core CPUs and hexa-core GPU for high-performance and energy-efficient mobile application processor." Solid-State Circuits Conference-(ISSCC), 2015 IEEE International. IEEE, 2015