From WikiChip
R-Car M1S - Renesas
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R-Car M1S | |||||||||||
General Info | |||||||||||
Designer | Renesas | ||||||||||
Manufacturer | TSMC | ||||||||||
Model Number | M1S | ||||||||||
Part Number | R8A77780 | ||||||||||
Market | Embedded | ||||||||||
Introduction | February 16, 2011 (announced) June, 2012 (launched) | ||||||||||
Release Price | $65 | ||||||||||
General Specs | |||||||||||
Family | R-Car | ||||||||||
Series | 1st Gen | ||||||||||
Frequency | 800 MHz | ||||||||||
Microarchitecture | |||||||||||
ISA | SuperH (SuperH) | ||||||||||
Microarchitecture | SH-4A | ||||||||||
Core Name | SH-4A | ||||||||||
Process | 40 nm | ||||||||||
Technology | CMOS | ||||||||||
Word Size | 32 bit | ||||||||||
Cores | 1 | ||||||||||
Threads | 1 | ||||||||||
Max Memory | 1 GiB | ||||||||||
Electrical | |||||||||||
Vcore | 1.2 V | ||||||||||
VI/O | 3.3 V | ||||||||||
Packaging | |||||||||||
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R-Car M1S is a mid-range performance embedded single-core SoC for the automotive industry designed by Renesas and introduced in 2011. The M1S features a single SH-4A core operating at 800 MHz. This chip incorporates Imagination's PowerVR SGX540 GPU operating at 200 MHz. This SoC supports up to 1 GiB of DDR3-1066 memory.
Introduced early-2011 with samples available in May 2011. Renesas expected mass production to begin in June 2012.
Cache
- Main article: Cortex-A9 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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- MLB (MOST150) 6-Pin I/F
- 2 x CAN 32 Message Buffers
- MMC
- 3 x SD
Graphics
- 20MPoly/s; 1000MPix/s; 3.2GFlops/s
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Integrated Graphics Information
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Block Diagram
Facts about "R-Car M1S - Renesas"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | R-Car M1S - Renesas#package + |
base frequency | 800 MHz (0.8 GHz, 800,000 kHz) + |
core count | 1 + |
core name | SH-4A + |
core voltage | 1.2 V (12 dV, 120 cV, 1,200 mV) + |
designer | Renesas + |
family | R-Car + |
first announced | February 16, 2011 + |
first launched | June 2012 + |
full page name | renesas/r-car/m1s + |
has ecc memory support | false + |
instance of | microprocessor + |
integrated gpu | PowerVR SGX540 + |
integrated gpu base frequency | 200 MHz (0.2 GHz, 200,000 KHz) + |
integrated gpu designer | Imagination Technologies + |
integrated gpu execution units | 2 + |
io voltage | 3.3 V (33 dV, 330 cV, 3,300 mV) + |
isa | SuperH + |
isa family | SuperH + |
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ description | 4-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
ldate | June 2012 + |
manufacturer | TSMC + |
market segment | Embedded + |
max memory | 1,024 MiB (1,048,576 KiB, 1,073,741,824 B, 1 GiB, 9.765625e-4 TiB) + |
max memory bandwidth | 3.97 GiB/s (4,065.28 MiB/s, 4.263 GB/s, 4,262.755 MB/s, 0.00388 TiB/s, 0.00426 TB/s) + |
max memory channels | 1 + |
microarchitecture | SH-4A + |
model number | M1S + |
name | R-Car M1S + |
package | FCBGA-472 + |
part number | R8A77780 + |
process | 40 nm (0.04 μm, 4.0e-5 mm) + |
release price | $ 65.00 (€ 58.50, £ 52.65, ¥ 6,716.45) + |
series | 1st Gen + |
supported memory type | DDR3-1066 + and DDR2-800 + |
technology | CMOS + |
thread count | 1 + |
word size | 32 bit (4 octets, 8 nibbles) + |