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Cooper Lake - Microarchitectures - Intel
Edit Values | |
Cooper Lake µarch | |
General Info | |
Arch Type | CPU |
Designer | Intel |
Manufacturer | Intel |
Introduction | June 18, 2020 |
Process | 14 nm++ |
Core Configs | 28, 24, 20, 18, 16, 8 |
Pipeline | |
Type | Superscalar |
OoOE | Yes |
Speculative | Yes |
Reg Renaming | Yes |
Stages | 14-19 |
Instructions | |
ISA | x86-64 |
Extensions | MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX, AVX-512 |
Cache | |
L1I Cache | 32 KiB/core 8-way set associative |
L1D Cache | 32 KiB/core 8-way set associative |
L1 Cache | 64 KiB/core |
L2 Cache | 1 MiB/Core 16-way set associative |
L3 Cache | 1.375 MiB/core 11-way set associative |
Cores | |
Core Names | Cooper Lake X, Cooper Lake SP, Cooper Lake AP |
Succession | |
Contemporary | |
Ice Lake (Server) Coffee Lake |
Cooper Lake (CPL / CPX) is Intel's successor to Cascade Lake, a 14 nm microarchitecture for the multiprocessing server market only.
Launched in mid-2020, Cooper Lake covers the 4-way and 8-way multiprocessing segments while Ice Lake serves the single and dual-socket segments.
For scalable server class processors, Intel branded it as Xeon Gold and Xeon Platinum.
Contents
Codenames
Single and dual-socket Cooper Lake parts were scrapped before ever making it to market.
Core | Abbrev | Target |
---|---|---|
Cooper Lake X | CPL-X | High-end desktops & enthusiasts market |
Cooper Lake W | CPL-W | Enterprise/Business workstations |
Cooper Lake SP | CPL-SP | Server Scalable Processors |
Cooper Lake AP | CPL-AP | Server Advanced Processors |
Brands
This section is empty; you can help add the missing info by editing this page. |
Release Dates
Cooper was first publicly disclosed in early 2019. Cooper Lake launched on June 18, 2020.
Process Technology
Cooper Lake is fabricated on Intel's 3rd generation enhanced 14nm++ process.
Architecture
Key changes from Cascade Lake
- SoC
- 2x UPI links (6, up from 3)
- Memory
- Higher data rate (3200 MT/s, up from 2933 MT/s)
- Optane DC DIMMs
- Apache Pass → Barlow Pass
- Platform
- Packaging
- Socket-P+
- 4189-contact flip-chip LGA (up from 3647 contacts)
- Socket-P+
This list is incomplete; you can help by expanding it.
New instructions
Cooper Lake introduced a number of new instructions:
- BFLOAT16 - A new data type for acceleration of AI workloads.
- AVX512 BF16 - AVX-512 Brain Float 16 extension
See also
Facts about "Cooper Lake - Microarchitectures - Intel"
codename | Cooper Lake + |
core count | 28 +, 24 +, 20 +, 18 +, 16 + and 8 + |
designer | Intel + |
first launched | June 18, 2020 + |
full page name | intel/microarchitectures/cooper lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Cooper Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |