From WikiChip
Package FP2 - AMD
Edit Values | |
Package FP2 | |
General Info | |
Designer | AMD |
Introduction | May 15, 2012 (launched) |
Market | Mobile, Embedded |
Microarchitecture | Piledriver |
TDP | 25 W 25,000 mW 0.0335 hp 0.025 kW |
Package | |
Name | FP2, BGA-827 |
Type | Organic Micro Ball Grid Array |
Contacts | 827 |
Dimension | 31 mm 3.1 cm × 27 mm1.22 in 2.7 cm 1.063 in |
Pitch | 0.8 mm 0.0315 in |
FP2 was a BGA-827 package for AMD mobile and embedded microprocessors with integrated graphics, the BGA counterpart to the PGA-722 package for Socket FS1r2. For desktop processors AMD developed Socket FM2. FP2 was superseded by the FP3 package.
Package FP2 was used in AMD's "Comal" mobile platform. All processors in the FP2 package, codename "Trinity" and "Richland", are members of AMD's Family 15h with CPU cores based on the Piledriver microarchitecture, and were fabricated on a 32 nm SOI process.
Contents
Features
- 827-pin lidless micro ball grid array package, 0.8-1.2 mm multi-pitch, 31 × 27 mm, organic substrate
- 2 × 64 bit DDR3 SDRAM interface up to 800 MHz, PC3-12800 (DDR3-1600), 25.6 GB/s
- Up to 2 SR UDIMMs or SODIMMs (1 per channel), no ECC support
- JEDEC 1.5V, 1.35V, 1.25V
- AMD Memory Controller PowerCap
- PCIe Gen 1.0 and 2.0 (5 GT/s)
- Configurable x8 or x16 external graphics card (GFX) link
- Configurable x4 General Purpose Ports
- x4 Unified Media Interface to FCH
- Four independent display controllers
- Six Digital Display Interfaces
- 3 × single link
- 3 × multiplexed, presumably each with 1x4 (dual link DVI 1x8) GFX lanes or 1x4 UMI lanes
- DisplayPort 1.2 up to 4096 × 2160 at 30 Hz and 30 bpp, eDP, DP++, DP audio, HDCP
- Single/dual link DVI 1.4a up to 2560 × 1600 at 60 Hz and 24 bpp, HDCP
- HDMI 1.4a up to 1920 × 1200 at 60 Hz and 24 bpp, 3D Video, HDCP
- VGA via FCH DP-DAC
- Six Digital Display Interfaces
- Power Management
- AMD AllDay power technology
- ACPI P-states, processor power states C0, C1, C1E, C6, sleep states S0, S3, S4, S5
- PCIe core power gating
- PCIe speed power policy
- AMD Turbo CORE technology 3.0 with per core power gating
- Thermal Controls
- Sideband temperature control (SB-TSI)
- Hardware thermal control (HTC)
- Local hardware thermal control (LHTC)
- DRAM thermal protection
Chipsets
- AMD FCH A50M/A60M/A55T/A70M/A68M, codename "Hudson-M1/M2/M2T/M3/M3L"
- AMD FCH A76M, codename "Bolton-M3"
Processors using package FP2
- AMD A-Series 4000 Mobile APU
- AMD A-Series 5000 Mobile APU
- AMD Embedded R-Series APU
List of all FP2-based Processors | |||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Model | Price | Process | Launched | µarch | Family | Core | C | T | Freq | Turbo | TDP | ||||||||
Count: 0 |
Package Diagram
Approximate dimensions of the Trinity package. All dimensions in millimeters.
FP2 package ball numbers.
Pin Map
References
- "Family 15h Models 10h - 1Fh AMD A-Series Mobile Accelerated Processor Product Data Sheet", AMD Publ. #50909, Rev. 3.03, November 29, 2012
- "Family 15h Models 10h - 1Fh AMD Embedded R-Series Accelerated Processor Product Data Sheet", AMD Publ. #51309, Rev. 3.01, November 28, 2012
- "Revision Guide for AMD Family 15h Models 10h-1Fh Processors", AMD Publ. #48931, Rev. 3.10, May 2013
- "Product Brief: AMD Embedded R-Series Platform", AMD Publ. #51954, Rev. C, 2013
See also
Facts about "Package FP2 - AMD"
designer | AMD + |
first launched | May 15, 2012 + |
instance of | package + |
market segment | Mobile + and Embedded + |
microarchitecture | Piledriver + |
name | Package FP2 + |
package | FP2 + and BGA-827 + |
package contacts | 827 + |
package length | 31 mm (3.1 cm, 1.22 in) + |
package pitch | 0.8 mm (0.0315 in) + |
package type | Organic Micro Ball Grid Array + |
package width | 27 mm (2.7 cm, 1.063 in) + |
tdp | 25 W (25,000 mW, 0.0335 hp, 0.025 kW) + |