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Alchemy Au1500-333MBC
General Info
Designer	Alchemy
Manufacturer	TSMC
Model Number	Au1500-333MBC
Part Number	Au1500-333MBC
Market	Embedded
Introduction	June 11, 2001 (announced) December 2001 (launched)
Release Price	$39 (tray)
General Specs
Family	Alchemy
Frequency	333 MHz
Microarchitecture
ISA	MIPS32
Microarchitecture	Au1
Core Stepping	AB, AC, AD
Process	180 nm
Technology	CMOS
Word Size	32 bit
Cores	1
Max Memory	192 MiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
Vcore	1.5 V ± 5%
VI/O	3.3 V
TDP (Typical)	400 mW
Tcase	0 °C – 70 °C
Tstorage	-40 °C – 125 °C

Au1500-333MBC was a 32-bit ultra low power embedded microprocessor with an Au1 CPU core implementing the MIPS32 ISA. Designed by Alchemy Semiconductor and fabricated on a TSMC 180 nm LV process, this SoC operates at a base frequency of up to 333 MHz with a typical TDP of 400 mW. It was also available with an industrial temperature range as Au1500-333MBI and a Pb-free version Au1500-333MBD.

Cache

Main article: Au1 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 32 KiB 32,768 B 0.0313 MiB L1I$ 16 KiB 16,384 B 0.0156 MiB 1 × 16 KiB 4-way set associative   L1D$ 16 KiB 16,384 B 0.0156 MiB 1 × 16 KiB 4-way set associative write-back

Memory controller

Au1500 processors integrate two independent memory controllers, a DRAM controller which supports SDRAM, SMROM, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, PCMCIA/CompactFlash devices, and I/O peripherals such as an external LCD controller. SDRAM runs at one half of the frequency of the internal 32-bit System Bus, which runs at up to one half of the CPU core frequency.

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type SDR-133 Supports ECC No Max Mem 192 MiB Controllers 1 Channels 1 Width 32 bit Max Bandwidth 0.333 GB/s 0.31 GiB/s 317.574 MiB/s 333 MB/s 3.028617e-4 TiB/s 3.33e-4 TB/s

Expansions

• PCI 2.2 controller, 32-bit bus, 33 or 66 MHz
• USB 1.1 (OHCI) host controller, USB 1.1 device controller
  • Two USB host ports and one device port
• Two 10/100 Mbit/s Ethernet MAC controllers
• Low speed interfaces AC97, 2 × UART, and up to 39 GPIOs

Graphics

This processor has no integrated graphics processing unit.

Features

• 8-channel DMA engine
• RTC and TOY timer
• Two interrupt controllers
• Power management unit
• MIPS EJTAG interface
• Idle Mode, Sleep Mode

Package

• 424-pin low profile, fine pitch plastic ball grid array (LF-PBGA) package
• 23 × 23 grid, 0.8 mm pitch, solder ball ⌀ 0.4 mm, 63Sn/37Pb
• 19 mm × 19 mm × 1.45 mm

Bibliography

• "Product Brief: AMD Alchemy™ Solutions Au1500™ Processor Family Internet Edge Processor", AMD Publ. #26329, Rev. D, 2003
• "AMD Alchemy™ Au1500™ Processor Data Book", AMD Publ. #30361, Rev. D, March 2006
• "AMD Alchemy™ Au1500™ Processor Specification Update", AMD Publ. #27362, Rev. E, June 2005
• "Qualification of the AMD Alchemy™ Au1500™ Processor", AMD Publ. #27364, Rev. B, March 2003
• Bassett, Paul. "Alchemy Au1x00", Hot Chips 14, August 19, 2002