Edit Values | |
Embedded G-Series T24L | |
General Info | |
Designer | AMD |
Manufacturer | TSMC |
Model Number | T24L |
Part Number | GET24LFQB12GVE |
Market | Embedded |
Introduction | March 1, 2011 (launched) |
End-of-life | 2021-Q2 (last order) 2021-Q4 (last shipment) |
Shop | Amazon |
General Specs | |
Family | Embedded G-Series |
Series | G-Series APU/CPU |
Frequency | 1,000 MHz |
Clock multiplier | 10 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Bobcat |
Core Name | eBrazos |
Core Family | 20 |
Process | 40 nm |
Transistors | 451,000,000 |
Technology | CMOS |
Die | 75 mm² |
Word Size | 64 bit |
Cores | 1 |
Threads | 1 |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
TDP | 5 W |
Tjunction | 0 °C – 90 °C |
Packaging | |
Template:packages/amd/FT1 |
T24L is a 64-bit single-core x86 embedded microprocessor introduced by AMD in March 2011. This processor is a member of the AMD Embedded G-Series formerly codenamed "eBrazos" with CPU cores based on the Bobcat microarchitecture and is fabricated on a TSMC 40 nm process. The T24L operates at a base frequency of 1.0 GHz with a TDP of 5 W. It supports single-channel DDR3-1066 memory.
Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
"eBrazos" processors integrate one 5-port, 8-lane PCIe Gen 1/2 (5 GT/s) controller. Four GPP lanes are configurable as up to four x4/x2/x1 wide (e.g. 1x2 + 2x1) links, the remaining four lanes are reserved for a UMI link to the chipset. The recommended AMD A50M "Hudson-M1" and A55E "Hudson-E1" controller hubs provide four PCIe Gen 1/2 lanes configurable as up to four x4/x2/x1 links, a 32-bit, 33 MHz PCI interface (A55E only), 6 × SATA Gen 1/2/3 (6 Gb/s), 14 × USB 1.1/2.0, 2 × USB 1.1, a Gb Ethernet MAC (A55E), HDA, LPC, SPI, SMBus, GPIO.
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Expansion Options |
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Features
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Bibliography
- "Product Brief: AMD Embedded G-Series APU Platform", AMD Publ. #49282, 2013
- "BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 14h Models 00h-0Fh Processors", AMD Publ. #43170, Rev. 3.13, February 17, 2012
- "Revision Guide for AMD Family 14h Models 00h-0Fh Processors", AMD Publ. #47534, Rev. 3.18, February 26, 2013
- Burgess, Brad. "“Bobcat” AMD’s New Low Power x86 Core Architecture", Hot Chips 22, August 24, 2010
- Burgess, Brad et al. (2011). Bobcat: AMD’s Low-Power x86 Processor. IEEE Micro. 31 (2): 16-25. doi:10.1109/MM.2011.2
- Foley, Denis et al. (2011). A Low-Power Integrated x86–64 and Graphics Processor for Mobile Computing Devices. IEEE JSSC. 47 (1): 220-231. doi:10.1109/JSSC.2011.2167776
- Rogers, Aaron; Kaplan, David; Quinnell, Eric; Kwan, Bill (2012). The Core-C6 (CC6) Sleep State of the AMD Bobcat x86 Microprocessor. ACM/IEEE ISLPED 2012. pp. 367-372. doi:10.1145/2333660.2333745
- "AMD Furthers Commitment to Embedded Customers With New Products and Expanded Support for Sales, Design and Software" (Press release). AMD.com. March 1, 2011.
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Embedded G-Series T24L - AMD#pcie + |
base frequency | 1,000 MHz (1 GHz, 1,000,000 kHz) + |
clock multiplier | 10 + |
core count | 1 + |
core family | 20 + |
core name | eBrazos + |
designer | AMD + |
die area | 75 mm² (0.116 in², 0.75 cm², 75,000,000 µm²) + |
family | Embedded G-Series + |
first launched | March 1, 2011 + |
full page name | amd/embedded/t24l + |
has amd amd-v technology | true + |
has ecc memory support | false + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l1i$ description | 2-way set associative + |
l1i$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
ldate | March 1, 2011 + |
manufacturer | TSMC + |
market segment | Embedded + |
max cpu count | 1 + |
max junction temperature | 363.15 K (90 °C, 194 °F, 653.67 °R) + |
max memory bandwidth | 7.944 GiB/s (8,134.842 MiB/s, 8.53 GB/s, 8,530 MB/s, 0.00776 TiB/s, 0.00853 TB/s) + |
max memory channels | 1 + |
microarchitecture | Bobcat + |
min junction temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
model number | T24L + |
name | Embedded G-Series T24L + |
package | FT1 + and UOB413 + |
part number | GET24LFQB12GVE + |
process | 40 nm (0.04 μm, 4.0e-5 mm) + |
series | G-Series APU/CPU + |
smp max ways | 1 + |
supported memory type | DDR3-1066 + |
tdp | 5 W (5,000 mW, 0.00671 hp, 0.005 kW) + |
technology | CMOS + |
thread count | 1 + |
transistor count | 451,000,000 + |
word size | 64 bit (8 octets, 16 nibbles) + |