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Alchemy Au1000-500MCC | |
General Info | |
Designer | Alchemy |
Manufacturer | TSMC |
Model Number | Au1000-500MCC |
Part Number | Au1000-500MCC |
Market | Embedded |
Introduction | June 13, 2000 (announced) February 2001 (launched) |
General Specs | |
Family | Alchemy |
Frequency | 500 MHz |
Microarchitecture | |
ISA | MIPS32 |
Microarchitecture | Au1 |
Core Stepping | DA, HA, HB, HC, HD |
Process | 180 nm |
Technology | CMOS |
Word Size | 32 bit |
Cores | 1 |
Max Memory | 192 MiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
Vcore | 1.8 V ± 5% |
VI/O | 3.3 V |
TDP (Typical) | 900 mW |
Tcase | 0 °C – 85 °C |
Tstorage | -40 °C – 125 °C |
Au1000-500MCC was a 32-bit ultra low power embedded microprocessor with an Au1 CPU core implementing the MIPS32 ISA. Designed by Alchemy Semiconductor and fabricated on a TSMC 180 nm LV process, this SoC operates at a base frequency of up to 500 MHz with a typical TDP of 900 mW.
Cache
- Main article: Au1 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Au1000 processors integrate two independent memory controllers, a DRAM controller which supports SDRAM, SMROM, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, PCMCIA/CompactFlash devices, and I/O peripherals such as an external LCD controller. SDRAM runs at one half of the frequency of the internal 32-bit System Bus, which runs at up to one half of the CPU core frequency.
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Integrated Memory Controller
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Expansions
- USB 1.1 (OHCI) host controller, USB 1.1 device controller
- Two USB host ports and one device port
- Two 10/100 Mbit/s Ethernet MAC controllers
- Low speed interfaces AC97, I2S, Fast IrDA, 2 × SSI, 4 × UART, and up to 32 GPIOs
Graphics
This processor has no integrated graphics processing unit.
Features
- 8-channel DMA engine
- RTC and TOY timer
- Two interrupt controllers
- Power management unit
- MIPS EJTAG interface
- Idle Mode, Sleep Mode
Package
- 324-pin low profile, fine pitch plastic ball grid array (LF-PBGA) package
- 22 × 22 grid, 1.0 mm pitch
- 23 mm × 23 mm × 1.5 mm
Bibliography
- "Product Brief: The Alchemy Au1000™ Internet Edge Processor", Alchemy, 2000
- "Product Brief: AMD Alchemy™ Solutions Au1000™ Processor Family Internet Edge Processor", AMD Publ. #26328, Rev. E, 2003
- "AMD Alchemy™ Au1000™ Processor Data Book", AMD Publ. #30360, Rev. D, September 2005
- "AMD Alchemy™ Au1000™ Processor Specification Update", AMD Publ. #27348, Rev. E, June 2005
- Hoeppner, Greg. "Au1000 Internet Edge Processor", Embedded Processor Forum 2000, June 13, 2000
- Plummer, Suzanne. "The Au1000™ Internet Edge Processor: A High Performance, Low Power SOC", Hot Chips 12, August 13, 2000
- Bassett, Paul. "Alchemy Au1x00", Hot Chips 14, August 19, 2002
base frequency | 500 MHz (0.5 GHz, 500,000 kHz) + |
core count | 1 + |
core stepping | DA +, HA +, HB +, HC + and HD + |
core voltage | 1.8 V (18 dV, 180 cV, 1,800 mV) + |
core voltage tolerance | 5% + |
designer | Alchemy + |
family | Alchemy + |
first announced | June 13, 2000 + |
first launched | February 2001 + |
full page name | alchemy/au1000-500mcc + |
has ecc memory support | false + |
instance of | microprocessor + |
io voltage | 3.3 V (33 dV, 330 cV, 3,300 mV) + |
isa | MIPS32 + |
l1$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l1d$ description | 4-way set associative + |
l1d$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
ldate | February 2001 + |
manufacturer | TSMC + |
market segment | Embedded + |
max case temperature | 358.15 K (85 °C, 185 °F, 644.67 °R) + |
max cpu count | 1 + |
max memory | 192 MiB (196,608 KiB, 201,326,592 B, 0.188 GiB, 1.831055e-4 TiB) + |
max memory bandwidth | 0.466 GiB/s (476.837 MiB/s, 0.5 GB/s, 500 MB/s, 4.547474e-4 TiB/s, 5.0e-4 TB/s) + |
max memory channels | 1 + |
max storage temperature | 398.15 K (125 °C, 257 °F, 716.67 °R) + |
microarchitecture | Au1 + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
min storage temperature | 233.15 K (-40 °C, -40 °F, 419.67 °R) + |
model number | Au1000-500MCC + |
name | Alchemy Au1000-500MCC + |
part number | Au1000-500MCC + |
process | 180 nm (0.18 μm, 1.8e-4 mm) + |
smp max ways | 1 + |
supported memory type | SDR-133 + |
tdp (typical) | 0.9 W (900 mW, 0.00121 hp, 9.0e-4 kW) + |
technology | CMOS + |
word size | 32 bit (4 octets, 8 nibbles) + |