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Cortex-A57 µarch
General Info
Arch Type	CPU
Designer	ARM Holdings
Manufacturer	TSMC
Introduction	Oct 30, 2012
Instructions
ISA	ARMv8
Succession
Cortex-A15 Cortex-A72

Cortex-A57 (codename Atlas) is the successor to the Cortex-A15, a low-power high-performance ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A57, which implemented the ARMv8 ISA, is the a performant core which is often combined with a number of lower power cores (e.g. Cortex-A53) in a big.LITTLE configuration to achieve better energy/performance.

Compiler support

Compiler	Arch-Specific	Arch-Favorable
Arm Compiler	-mcpu=cortex-a57	-mtune=cortex-a57
GCC	-mcpu=cortex-a57	-mtune=cortex-a57
LLVM	-mcpu=cortex-a57	-mtune=cortex-a57

If the Cortex-A57 is coupled with the Cortex-A53 in a big.LITTLE system, GCC also supports the following option:

Compiler	Tune
GCC	-mtune=cortex-a57.cortex-a53

Architecture

Key changes from Cortex-A15

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Block Diagram

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Memory Hierarchy

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Die

Cortex-A57 Clusters Silicon Areas (Estimated)
Company	Samsung	Renesas
Chip	Exynos 5433	R-Car H3
Process	20 nm	16 nm
Configuration	4x Cortex-A57 + 2 MiB L2	4x Cortex-A57 + 2 MiB L2
Cluster Size	~15.85 mm²	~10.21 mm² cluster
Core Size	~3 mm²	~1.66 mm² cluster
Cache Size	~3.87 mm²	~3.28 mm² cluster

20 nm

Samsung Exynos 5433

• Samsung 20 nm process
• 113 mm² die size
• Mali-T760 (6 EU)
• Quad-core {Primary Cortex-A57 [Quad] + Secondary A53 [Quad]}
  • 32 KiB L1I$ and 32 KiB L1D$ per core, and a shared 256 KiB L2
  • 4.4 mm² per cluster
    • ~1 mm² per core
    • ~0.55 mm² for 256 KiB L2 cache
• Quad-core Cortex-A57 (big cores)
  • 48KB L1I$ and 32KB L1D$ per core, and a shared 2 MiB L2
  • 15.85 mm² per cluster
    • ~3 mm² per core
    • ~3.87 mm² for 2 MiB L2 cache

16 nm

Renesas R-Car H3

• TSMC 16 nm process
• 12.94 mm × 8.61 mm
• 111.36 mm² die size
• Quad-core Cortex-A53
  • ~3.27 mm² cluster
  • ~0.60 mm² core
  • ~0.7 mm² 512 KiB L2 cache
• Quad-core Cortex-A57
  • ~10.21 mm² cluster
  • ~1.66 mm² core
  • ~3.28 mm² 2 MiB L2 cache
• Cortex-R7 (dual-core lock-step)
  • ~1.04 mm² cluster
• GX6650 GPU
  • ~28.12 mm²

A57 Cluster:

Bibliography

• Pyo, Jungyul, et al. "23.1 20nm high-K metal-gate heterogeneous 64b quad-core CPUs and hexa-core GPU for high-performance and energy-efficient mobile application processor." Solid-State Circuits Conference-(ISSCC), 2015 IEEE International. IEEE, 2015