From WikiChip
NNP-I 1100 - Intel Nervana
< nervana‎ | nnp
Revision as of 00:42, 1 February 2020 by David (talk | contribs)

Edit Values
NNP-I 1100
spring hill package (front).png
General Info
DesignerIntel
ManufacturerIntel
Model NumberNNP-I 1100
MarketServer, Edge
IntroductionNovember 12, 2019 (announced)
November 12, 2019 (launched)
ShopAmazon
General Specs
FamilyNNP
SeriesNNP-I
Microarchitecture
MicroarchitectureSpring Hill
Process10 nm
Transistors8,500,000,000
TechnologyCMOS
Die239 mm²
Cores12
Electrical
TDP12 W
Packaging
spring hill package (back).png

NNP-I 1100 is an inference neural processor designed by Intel Nervana and introduced in late 2019. Fabricated on Intel's 10 nm process based on the Spring Hill microarchitecture, the NNP-I 1100 has 12 ICEs for a peak performance of 50 TOPS at a TDP of 12 W. This chip comes in an M.2 accelerator card form factor.

Retrieved from "https://en.wikichip.org/w/index.php?title=nervana/nnp/nnp-i_1100&oldid=95686"
Facts about "NNP-I 1100 - Intel Nervana"
RDF feed
back imageFile:spring hill package (back).png +
core count12 +
designerIntel +
die area239 mm² (0.37 in², 2.39 cm², 239,000,000 µm²) +
familyNNP +
first announcedNovember 12, 2019 +
first launchedNovember 12, 2019 +
full page namenervana/nnp/nnp-i 1100 +
has ecc memory supporttrue +
instance ofmicroprocessor +
ldateNovember 12, 2019 +
main imageFile:spring hill package (front).png +
manufacturerIntel +
market segmentServer + and Edge +
max memory bandwidth62.585 GiB/s (64,086.914 MiB/s, 67.2 GB/s, 67,200 MB/s, 0.0611 TiB/s, 0.0672 TB/s) +
microarchitectureSpring Hill + and Sunny Cove +
model numberNNP-I 1100 +
nameNNP-I 1100 +
peak integer ops (8-bit)50,000,000,000,000 OPS (50,000,000,000 KOPS, 50,000,000 MOPS, 50,000 GOPS, 50 TOPS, 0.05 POPS, 5.0e-5 EOPS, 5.0e-8 ZOPS) +
process10 nm (0.01 μm, 1.0e-5 mm) +
seriesNNP-I +
supported memory typeLPDDR4X-4200 +
tdp12 W (12,000 mW, 0.0161 hp, 0.012 kW) +
technologyCMOS +
transistor count8,500,000,000 +