Xeon Gold 6140 - Intel

	Edit Values
	Xeon Gold 6140
	General Info
Designer	Intel
Manufacturer	Intel
Model Number	6140
Part Number	BX806736140,; CD8067303405200
S-Spec	SR3AX; QMRS (QS)
Market	Server
Introduction	April 25, 2017 (announced); July 11, 2017 (launched)
Release Price	$2445.00
Shop	Amazon
	General Specs
Family	Xeon Gold
Series	6100
Locked	Yes
Frequency	2,300 MHz
Turbo Frequency	3,700 MHz (1 core)
Bus type	DMI 3.0
Bus rate	4 × 8 GT/s
Clock multiplier	23
CPUID	0x50654
	Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Skylake (server)
Platform	Purley
Chipset	Lewisburg
Core Name	Skylake SP
Core Family	6
Core Stepping	H0
Process	14 nm
Technology	CMOS
Word Size	64 bit
Cores	18
Threads	36
Max Memory	768 GiB
	Multiprocessing
Max SMP	4-Way (Multiprocessor)
Interconnect	UPI
Interconnect Links	3
Interconnect Rate	10.4 GT/s
	Electrical
TDP	140 W
Tcase	0 °C – 91 °C
TDTS	0 °C – 101 °C
	Packaging
Package	FCLGA-3647 (FCLGA)
Dimension	76.16 mm × 56.6 mm
Pitch	0.8585 mm × 0.9906 mm
Contacts	3647
Socket	Socket P, LGA-3647
	Succession
	Xeon Gold 6240

Xeon Gold 6140 is a 64-bit 18-core x86 multi-socket high performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6140, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 2.3 GHz with a TDP of 140 W and a turbo boost frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.

Cache[edit]

Main article: Skylake § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

1.125 MiB

1,152 KiB
1,179,648 B

L1I$	576 KiB 589,824 B 0.563 MiB	18x32 KiB	8-way set associative
L1D$	576 KiB 589,824 B 0.563 MiB	18x32 KiB	8-way set associative	write-back

L2$

18 MiB

18,432 KiB
18,874,368 B
0.0176 GiB

		18x1 MiB	16-way set associative	write-back

L3$

24.75 MiB

25,344 KiB
25,952,256 B
0.0242 GiB

		18x1.375 MiB	11-way set associative	write-back

Memory controller[edit]

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	DDR4-2666
Supports ECC	Yes
Max Mem	768 GiB
Controllers	2
Channels	6
Max Bandwidth	119.21 GiB/s 122,071.04 MiB/s 128.001 GB/s 128,000.763 MB/s 0.116 TiB/s 0.128 TB/s
Bandwidth	Single 19.87 GiB/s Double 39.74 GiB/s Quad 79.47 GiB/s Hexa 119.21 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

Expansion Options

PCIe

Revision	3.0
Max Lanes	48
Configs	x16, x8, x4

Features[edit]

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX	MMX Extension
EMMX	Extended MMX Extension
SSE	Streaming SIMD Extensions
SSE2	Streaming SIMD Extensions 2
SSE3	Streaming SIMD Extensions 3
SSSE3	Supplemental SSE3
SSE4.1	Streaming SIMD Extensions 4.1
SSE4.2	Streaming SIMD Extensions 4.2
AVX	Advanced Vector Extensions
AVX2	Advanced Vector Extensions 2
AVX-512	Advanced Vector 512-bit
AVX512F	AVX-512 Foundation
AVX512CD	AVX-512 Conflict Detection
AVX512BW	AVX-512 Byte and Word
AVX512DQ	AVX-512 Doubleword and Quadword Instructions
AVX512VL	AVX-512 Vector Length
ABM	Advanced Bit Manipulation
BMI1	Bit Manipulation Instruction Set 1
BMI2	Bit Manipulation Instruction Set 2
FMA3	3-Operand Fused-Multiply-Add
AES	AES Encryption Instructions
RdRand	Hardware RNG
ADX	Multi-Precision Add-Carry
CLMUL	Carry-less Multiplication Extension
F16C	16-bit Floating Point Conversion

x86-16	16-bit x86
x86-32	32-bit x86
x86-64	64-bit x86
Real	Real Mode
Protected	Protected Mode
SMM	System Management Mode
FPU	Integrated x87 FPU
NX	No-eXecute
HT	Hyper-Threading
TBT 2.0	Turbo Boost Technology 2.0
EIST	Enhanced SpeedStep Technology
SST	Speed Shift Technology
TXT	Trusted Execution Technology (SMX)
vPro	Intel vPro
VT-x	VT-x (Virtualization)
VT-d	VT-d (I/O MMU virtualization)
EPT	Extended Page Tables (SLAT)
TSX	Transactional Synchronization Extensions
VMD	Volume Management Device
NM	Node Manager
KPT	Key Protection Technology
PTT	Platform Trust Technology
Run Sure	Run Sure Technology (RAS Capability)
MBE Ctrl	Mode-Based Execute Control
Node Ctrlr	Node Controller Support

Frequencies[edit]

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

Mode	Base	Turbo Frequency/Active Cores
Mode	Base	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18
Normal	2,300 MHz	3,700 MHz	3,700 MHz	3,500 MHz	3,500 MHz	3,400 MHz	3,400 MHz	3,400 MHz	3,400 MHz	3,400 MHz	3,400 MHz	3,400 MHz	3,400 MHz	3,100 MHz	3,100 MHz	3,100 MHz	3,100 MHz	3,000 MHz	3,000 MHz
AVX2	1,900 MHz	3,600 MHz	3,600 MHz	3,400 MHz	3,400 MHz	3,300 MHz	3,300 MHz	3,300 MHz	3,300 MHz	3,000 MHz	3,000 MHz	3,000 MHz	3,000 MHz	2,700 MHz	2,700 MHz	2,700 MHz	2,700 MHz	2,600 MHz	2,600 MHz
AVX512	1,500 MHz	3,500 MHz	3,500 MHz	3,300 MHz	3,300 MHz	2,800 MHz	2,800 MHz	2,800 MHz	2,800 MHz	2,400 MHz	2,400 MHz	2,400 MHz	2,400 MHz	2,100 MHz	2,100 MHz	2,100 MHz	2,100 MHz	2,100 MHz	2,100 MHz

Benchmarks[edit]

[Edit Benchmarks]

Test: SPEC CPU2017
Tested: 2017-09-30 09:14:46-0400
Chips: 4, Cores: 72, Threads: 72

Vendor: Cisco Systems
System: Cisco UCS C480 M5 (Intel Xeon Gold 6140, 2.30GHz)

SPECspeed2017_int_base: 8.87

SPECspeed2017_int_peak: 9.14

Test: SPEC CPU2017
Tested: 2017-09-30 14:18:40-0400
Chips: 4, Cores: 72, Threads: 72

Vendor: Cisco Systems
System: Cisco UCS C480 M5 (Intel Xeon Gold 6140, 2.30GHz)

SPECspeed2017_fp_base: 142

SPECspeed2017_fp_peak: 144

Test: SPEC CPU2017
Tested: 2017-10-24 12:43:08-0400
Chips: 2, Cores: 36, Threads: 36