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Xeon Gold 6126T
General Info
Designer	Intel
Manufacturer	Intel
Model Number	6126T
Part Number	CD8067303593100
S-Spec	SR3J9 QN39 (QS)
Market	Server
Introduction	April 25, 2017 (announced) July 11, 2017 (launched)
Release Price	$1865.00
Shop	Amazon
General Specs
Family	Xeon Gold
Series	6100
Locked	Yes
Frequency	2,600 MHz
Turbo Frequency	3,700 MHz (1 core)
Bus type	DMI 3.0
Bus rate	4 × 8 GT/s
Clock multiplier	26
CPUID	0x50654
Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Skylake (server)
Platform	Purley
Chipset	Lewisburg
Core Name	Skylake SP
Core Family	6
Core Stepping	H0
Process	14 nm
Technology	CMOS
Word Size	64 bit
Cores	12
Threads	24
Max Memory	768 GiB
Multiprocessing
Max SMP	4-Way (Multiprocessor)
Interconnect	UPI
Interconnect Links	3
Interconnect Rate	10.4 GT/s
Electrical
TDP	125 W
Tcase	0 °C – 74 °C
Packaging
Package	FCLGA-3647 (FCLGA)
Dimension	76.16 mm × 56.6 mm
Pitch	0.8585 mm × 0.9906 mm
Contacts	3647
Socket	Socket P, LGA-3647

Xeon Gold 6126T is a 64-bit dodeca-core x86 multi-socket high performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6126T, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 2.6 GHz with a TDP of 125 W and a turbo boost frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.

This specific model (T) has 10 years extended life guarantees designed to be NEBS-friendly for use in NEBS-complaint applications.

Cache

Main article: Skylake § Cache

The Xeon Gold 6126T features a considerably larger non-default 19.25 MiB of L3, a size that would normally be found on a 14-core part.

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 768 KiB 786,432 B 0.75 MiB L1I$ 384 KiB 393,216 B 0.375 MiB 12x32 KiB 8-way set associative   L1D$ 384 KiB 393,216 B 0.375 MiB 12x32 KiB 8-way set associative write-back L2$ 12 MiB 12,288 KiB 12,582,912 B 0.0117 GiB     12x1 MiB 16-way set associative write-back L3$ 19.25 MiB 19,712 KiB 20,185,088 B 0.0188 GiB     14x1.375 MiB 11-way set associative write-back

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR4-2666 Supports ECC Yes Max Mem 768 GiB Controllers 2 Channels 6 Max Bandwidth 119.21 GiB/s 122,071.04 MiB/s 128.001 GB/s 128,000.763 MB/s 0.116 TiB/s 0.128 TB/s Bandwidth Single 19.87 GiB/s Double 39.74 GiB/s Quad 79.47 GiB/s Hexa 119.21 GiB/s

Expansions

[Edit/Modify Expansions Info]

	Expansion Options
	PCIe Revision 3.0 Max Lanes 48 Configs x16, x8, x4

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX MMX Extension EMMX Extended MMX Extension SSE Streaming SIMD Extensions SSE2 Streaming SIMD Extensions 2 SSE3 Streaming SIMD Extensions 3 SSSE3 Supplemental SSE3 SSE4.1 Streaming SIMD Extensions 4.1 SSE4.2 Streaming SIMD Extensions 4.2 AVX Advanced Vector Extensions AVX2 Advanced Vector Extensions 2 AVX-512 Advanced Vector 512-bit AVX512F AVX-512 Foundation AVX512CD AVX-512 Conflict Detection AVX512BW AVX-512 Byte and Word AVX512DQ AVX-512 Doubleword and Quadword Instructions AVX512VL AVX-512 Vector Length ABM Advanced Bit Manipulation BMI1 Bit Manipulation Instruction Set 1 BMI2 Bit Manipulation Instruction Set 2 FMA3 3-Operand Fused-Multiply-Add AES AES Encryption Instructions RdRand Hardware RNG ADX Multi-Precision Add-Carry CLMUL Carry-less Multiplication Extension F16C 16-bit Floating Point Conversion x86-16 16-bit x86 x86-32 32-bit x86 x86-64 64-bit x86 Real Real Mode Protected Protected Mode SMM System Management Mode FPU Integrated x87 FPU NX No-eXecute HT Hyper-Threading TBT 2.0 Turbo Boost Technology 2.0 EIST Enhanced SpeedStep Technology SST Speed Shift Technology TXT Trusted Execution Technology (SMX) vPro Intel vPro VT-x VT-x (Virtualization) VT-d VT-d (I/O MMU virtualization) EPT Extended Page Tables (SLAT) TSX Transactional Synchronization Extensions VMD Volume Management Device NM Node Manager KPT Key Protection Technology PTT Platform Trust Technology Run Sure Run Sure Technology (RAS Capability) MBE Ctrl Mode-Based Execute Control Node Ctrlr Node Controller Support

Frequencies

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

Mode	Base	Turbo Frequency/Active Cores
		1	2	3	4	5	6	7	8	9	10	11	12
Normal	2,600 MHz	3,700 MHz	3,700 MHz	3,500 MHz	3,500 MHz	3,400 MHz	3,400 MHz	3,400 MHz	3,400 MHz	3,300 MHz	3,300 MHz	3,300 MHz	3,300 MHz
AVX2	2,200 MHz	3,600 MHz	3,600 MHz	3,400 MHz	3,400 MHz	3,300 MHz	3,300 MHz	3,300 MHz	3,300 MHz	2,900 MHz	2,900 MHz	2,900 MHz	2,900 MHz
AVX512	1,700 MHz	3,500 MHz	3,500 MHz	3,300 MHz	3,300 MHz	2,600 MHz	2,600 MHz	2,600 MHz	2,600 MHz	2,300 MHz	2,300 MHz	2,300 MHz	2,300 MHz