Edit Values |
z15 µarch |
|
Arch Type | CPU |
Designer | IBM |
Manufacturer | GlobalFoundries |
Introduction | September 12, 2019 |
Process | 14 nm |
Core Configs | 12 |
|
Type | Superscalar, Pipelined |
OoOE | Yes |
Speculative | Yes |
Reg Renaming | Yes |
|
ISA | z/Architecture |
|
L1I Cache | 128 KiB |
L1D Cache | 128 KiB |
|
|
z15 is the successor to the z14, a 14 nm z/Architecture mainframe microarchitecture designed by IBM and introduced in 2019.
Process Technology
IBM fabricates its z15 microprocessors and system controllers on GlobalFoundries's 14 nm (14HP) FinFET Silicon-On-Insulator (SOI) process featuring highly-dense deep trench structures used for high-density eDRAM.
Release Dates
The z15 was launched by IBM on September 12, 2019. General availability of the z15 mainframe started September 23.
Architecture
Key changes from z14
- Higher scalability
- Up to 190-way multiprocessing (from 170-way)
- Central Processor (CP)
- 2 more cores (12, up from 10)
- Core
- 10-13% higher IPC (IBM claim)
- Front-end
- Improved branch predictor
- New TAGE predictor
- BTB pre-buffer (BTBp) replaced by a simpler write buffer
- single double-bandwidth port (two independentread ports)
- 2x larger L1 BTB (8 sets of 2K rows, up from 4 sets of 2K rows)
- Back-end
- Larger GCT (60 groups, up from 48 groups)
- Wider retire (12 instructions/cycle, up from 10)
- Larger Issue Queues (2 x 36-entry, up from 2 x 30-entry)
- 2x larger mapper (128-entry, up from 64-entry)
- Larger integer physical register files (???, up from 120 entries)
- Larger vector physical register files (???, up from 127 entries)
- Execution engine
- New Modulo Arithmetic (MA) unit
- Memory subsystem
- Shared L3
- 2x larger L3 (256 MiB, up from 128 MiB)
- New integration
- Nest Acceleration Unit (NXU)
- System Controller (SC)
- 1.4x Larger L4 cache (960 MiB, up from 672 MiB)
Overview
Mainframe
System
Drawer
Central Processor
Core
Die
Central Processor (CP) Chip
Core
System Controller (SC) Chip