Xeon Platinum 9221 - Intel

	Edit Values
	Xeon Platinum 9221
	General Info
Designer	Intel
Manufacturer	Intel
Model Number	9221
Market	Server, HPC
Introduction	April 2, 2019 (announced); April 2, 2019 (launched)
Shop	Amazon
	General Specs
Family	Xeon Platinum
Series	9200
Locked	Yes
Frequency	2,100 MHz
Turbo Frequency	3,700 MHz (1 core)
Bus type	DMI 3.0
Bus rate	4 × 8 GT/s
Clock multiplier	21
	Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Cascade Lake
Platform	Walker Pass
Chipset	Lewisburg
Core Name	Cascade Lake AP
Core Family	6
Process	14 nm
Technology	CMOS
MCP	Yes (2 dies)
Word Size	64 bit
Cores	32
Threads	64
Max Memory	2 TiB
	Multiprocessing
Max SMP	2-Way (Multiprocessor)
	Electrical
TDP	250 W
	Packaging
Package	FCBGA-5903 (BGA)
Pitch	0.99 mm
Contacts	5903

Xeon Platinum 9221 is a 32-core 64-bit high-performance x86 server microprocessor introduced by Intel in early 2019. The 9221 is based on the Cascade Lake microarchitecture and is fabricated on Intel's 14 nm process. It operates at 2.1 GHz with a TDP of 250 W and a turbo boost of up to 3.7 GHz. This processor supports up to twelve channels of DDR4-2933 memory.

This processor cannot be purchased independently and is only sold as part of Intel's S9200WK Compute Module.

Cache[edit]

Main article: Cascade Lake § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

2 MiB

2,048 KiB
2,097,152 B

L1I$	1 MiB 1,024 KiB 1,048,576 B	32x32 KiB	8-way set associative
L1D$	1 MiB 1,024 KiB 1,048,576 B	32x32 KiB	8-way set associative	write-back

L2$

32 MiB

32,768 KiB
33,554,432 B
0.0313 GiB

		32x1 MiB	16-way set associative	write-back

L3$

71.5 MiB

73,216 KiB
74,973,184 B
0.0698 GiB

		52x1.375 MiB	11-way set associative	write-back

Memory controller[edit]

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	DDR4-2933
Supports ECC	Yes
Max Mem	2 TiB
Controllers	4
Channels	12
Max Bandwidth	262.26 GiB/s 268,554.24 MiB/s 281.6 GB/s 281,599.531 MB/s 0.256 TiB/s 0.282 TB/s
Bandwidth	Single 21.86 GiB/s Double 43.71 GiB/s Quad 87.42 GiB/s Octa 174.84 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

Expansion Options

PCIe	Revision: 3.0
	Max Lanes: 40
	Configuration: 1x16, x8, x4

Features[edit]

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX	MMX Extension
EMMX	Extended MMX Extension
SSE	Streaming SIMD Extensions
SSE2	Streaming SIMD Extensions 2
SSE3	Streaming SIMD Extensions 3
SSSE3	Supplemental SSE3
SSE4.1	Streaming SIMD Extensions 4.1
SSE4.2	Streaming SIMD Extensions 4.2
AVX	Advanced Vector Extensions
AVX2	Advanced Vector Extensions 2
AVX-512	Advanced Vector 512-bit
AVX512F	AVX-512 Foundation
AVX512CD	AVX-512 Conflict Detection
AVX512BW	AVX-512 Byte and Word
AVX512DQ	AVX-512 Doubleword and Quadword Instructions
AVX512VL	AVX-512 Vector Length
AVX512_VNNI	AVX-512 Vector Neural Network Instructions
ABM	Advanced Bit Manipulation
BMI1	Bit Manipulation Instruction Set 1
BMI2	Bit Manipulation Instruction Set 2
FMA3	3-Operand Fused-Multiply-Add
AES	AES Encryption Instructions
RdRand	Hardware RNG
ADX	Multi-Precision Add-Carry
CLMUL	Carry-less Multiplication Extension
F16C	16-bit Floating Point Conversion

x86-16	16-bit x86
x86-32	32-bit x86
x86-64	64-bit x86
Real	Real Mode
Protected	Protected Mode
SMM	System Management Mode
FPU	Integrated x87 FPU
NX	No-eXecute
HT	Hyper-Threading
TBT 2.0	Turbo Boost Technology 2.0
EIST	Enhanced SpeedStep Technology
SST	Speed Shift Technology
TXT	Trusted Execution Technology (SMX)
vPro	Intel vPro
VT-x	VT-x (Virtualization)
VT-d	VT-d (I/O MMU virtualization)
EPT	Extended Page Tables (SLAT)
TSX	Transactional Synchronization Extensions
VMD	Volume Management Device
NM	Node Manager
KPT	Key Protection Technology
PTT	Platform Trust Technology
Run Sure	Run Sure Technology (RAS Capability)
MBE Ctrl	Mode-Based Execute Control
Node Ctrlr	Node Controller Support

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon Platinum 9221 - Intel#pcie +
base frequency	2,100 MHz (2.1 GHz, 2,100,000 kHz) +
bus links	4 +
bus rate	8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus type	DMI 3.0 +
chipset	Lewisburg +
clock multiplier	21 +
core count	32 +
core family	6 +
core name	Cascade Lake AP +
designer	Intel +
die count	2 +
family	Xeon Platinum +
first announced	April 2, 2019 +
first launched	April 2, 2019 +
full page name	intel/xeon platinum/9221 +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables + and Transactional Synchronization Extensions +
has intel enhanced speedstep technology	true +
has intel speed shift technology	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
is multi-chip package	true +
isa	x86-64 +
isa family	x86 +
l1$ size	2,048 KiB (2,097,152 B, 2 MiB) +
l1d$ description	8-way set associative +
l1d$ size	1,024 KiB (1,048,576 B, 1 MiB) +
l1i$ description	8-way set associative +
l1i$ size	1,024 KiB (1,048,576 B, 1 MiB) +
l2$ description	16-way set associative +
l2$ size	32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) +
l3$ description	11-way set associative +
l3$ size	71.5 MiB (73,216 KiB, 74,973,184 B, 0.0698 GiB) +
ldate	April 2, 2019 +
main image	+
manufacturer	Intel +
market segment	Server + and HPC +
max cpu count	2 +
max memory	2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) +
max memory bandwidth	262.26 GiB/s (268,554.24 MiB/s, 281.6 GB/s, 281,599.531 MB/s, 0.256 TiB/s, 0.282 TB/s) +
max memory channels	12 +
microarchitecture	Cascade Lake +
model number	9221 +
name	Xeon Platinum 9221 +
package	FCBGA-5903 +
platform	Walker Pass +
process	14 nm (0.014 μm, 1.4e-5 mm) +
series	9200 +
smp max ways	2 +
supported memory type	DDR4-2933 +
tdp	250 W (250,000 mW, 0.335 hp, 0.25 kW) +
technology	CMOS +
thread count	64 +
turbo frequency (1 core)	3,700 MHz (3.7 GHz, 3,700,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +

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Contents

Cache[edit]

Memory controller[edit]

Expansions[edit]

Features[edit]