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From WikiChip
Lakefield - Microarchitectures - Intel
< intel | microarchitectures
Edit Values | |
Lakefield µarch | |
General Info | |
Arch Type | CPU |
Designer | Intel |
Manufacturer | Intel |
Introduction | 2019 |
Process | 22 nm, 10 nm |
Core Configs | 5 |
Pipeline | |
Type | Superscalar, Superpipeline |
OoOE | Yes |
Speculative | Yes |
Reg Renaming | Yes |
Instructions | |
ISA | x86-64 |
Cache | |
L2 Cache | 512 KiB + 1.5 MiB |
L3 Cache | 4 MiB/chip |
Lakefield (LKF) is a high-performance low-power 3D microarchitecture designed by Intel and introduced in 2019.
Architecture
- 3d integrated circuit
- Foveros packaging
- 22 nm base field
- 10 nm compute field
- 1x Sunny Cove big core
- 4x Tremont small cores
- GPU
- Gen11 graphics
- Memory
- LPDDR4X up to 4266 MT/s
- POP DRAM
Block diagram
This section is empty; you can help add the missing info by editing this page. |
Overview
This section is empty; you can help add the missing info by editing this page. |
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/lakefield&oldid=90687"
Hidden category:
Facts about "Lakefield - Microarchitectures - Intel"
codename | Lakefield + |
core count | 5 + |
designer | Intel + |
first launched | 2019 + |
full page name | intel/microarchitectures/lakefield + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Lakefield + |
process | 22 nm (0.022 μm, 2.2e-5 mm) + and 10 nm (0.01 μm, 1.0e-5 mm) + |