From WikiChip
Xeon Gold 6230T - Intel
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General Info | |
Microarchitecture |
Xeon Gold 6230T is a 64-bit 20-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 6230T is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 2.1 GHz with a TDP of 125 W and features a turbo boost frequency of up to 3.9 GHz.
Cache
- Main article: Cascade Lake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Facts about "Xeon Gold 6230T - Intel"
full page name | intel/xeon gold/6230t + |
has ecc memory support | true + |
instance of | microprocessor + |
l1$ size | 1,280 KiB (1,310,720 B, 1.25 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 640 KiB (655,360 B, 0.625 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 640 KiB (655,360 B, 0.625 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 20 MiB (20,480 KiB, 20,971,520 B, 0.0195 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 27.5 MiB (28,160 KiB, 28,835,840 B, 0.0269 GiB) + |
ldate | 1900 + |
max memory bandwidth | 131.13 GiB/s (134,277.12 MiB/s, 140.8 GB/s, 140,799.765 MB/s, 0.128 TiB/s, 0.141 TB/s) + |
max memory channels | 6 + |
supported memory type | DDR4-2933 + |