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General Info

Microarchitecture

Xeon Gold 6246 is a 64-bit 12-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 6246 is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 3.3 GHz with a TDP of 165 W and features a turbo boost frequency of up to 4.2 GHz.

Cache

Main article: Cascade Lake § Cache

The Xeon Gold 6246 features a considerably larger non-default 24.75 MiB of L3, a size that would normally be found on an 18-core part.

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 768 KiB 786,432 B 0.75 MiB L1I$ 384 KiB 393,216 B 0.375 MiB 12x32 KiB 8-way set associative   L1D$ 384 KiB 393,216 B 0.375 MiB 12x32 KiB 8-way set associative write-back L2$ 12 MiB 12,288 KiB 12,582,912 B 0.0117 GiB     12x1 MiB 16-way set associative write-back L3$ 24.75 MiB 25,344 KiB 25,952,256 B 0.0242 GiB     18x1.375 MiB 11-way set associative write-back